On chip real time FPN correction without imager size memory
View Patent ↗A circuit and method for correcting pixel output signals for fixed pattern noise. Pixels in a selected row of pixels are read after an integration period and the resulting signals are stored in a first sample and hold circuit for each column. The pixels in the selected row are then reset and immediately read again and the resulting signals are stored in a second sample and hold circuit for each column. The signals in the second sample and hold circuits are subtracted from the signals in the first sample and hold circuits to produce signals related to the light seen by the pixels in the selected row corrected for fixed pattern noise. The output of the first sample and hold circuits and second sample and hold circuits can be connected to a subtraction unit and sequentially activated so that a single subtraction unit is required for the entire imager. The output of the subtraction unit can connected to a buffer thereby storing signals corrected for fixed pattern noise in the buffer using only a single subtraction unit and avoiding the need for a large memory to store dark pixel signals.
1. A method of correcting for fixed pattern noise, comprising:
providing a pixel having a photodiode;
providing a first sample and hold circuit and a second sample and hold circuit, wherein said first sample and hold circuit and said second sample and hold circuit each comprise a first FET having a source, a drain, and a gate; a first capacitor having a first terminal connected to said drain of said first FET and a second terminal connected to ground potential; a second capacitor having a first terminal connected to said drain of said first FET and a second terminal; a second FET having a source connected to said second terminal of said second capacitor, a drain connected to ground potential, and a gate; and a third FET having a source connected to said source of said second FET, a gate, and a drain connected to an output bus;
allowing light to impinge on said photodiode during an integration period;
performing a first readout of said photodiode after said integration period has been completed and storing a first signal in said first sample and hold circuit wherein said first signal is related to the potential of said photodiode during said first readout of said photodiode;
resetting said photodiode after performing said first readout of said photodiode;
performing a second readout of said photodiode, after resetting said photodiode after performing said first readout of said photodiode, and storing a second signal in said second sample and hold circuit wherein said second signal is related to the potential of said photodiode during said second readout of said photodiode;
resetting said photodiode after said second readout of said photodiode to prepare for the next integration period;
subtracting said second signal from said first signal, thereby producing a signal related to the amount of light incident on said photodiode during said integration period corrected for fixed pattern noise.
2. The method of claim 1 wherein said resetting said photodiode comprises resetting the potential of said photodiode.
3. The method of claim 1 wherein said subtracting said second signal from said first signal can be accomplished in the digital domain or the analog domain.
4. A method of correcting for fixed pattern noise in an imager:
providing an imager having an array of N rows and M columns of pixels, wherein N and M are positive whole numbers and each pixel has a photodiode;
providing a first sample and hold circuit having an input and an output and a second sample and hold circuit having an input and an output for each of said columns of pixels, wherein a signal stored in said first sample and hold circuit is connected to said output of that said first sample and hold circuit and a signal stored in said second sample and hold circuit for the same said column of pixels is connected to said output of that said second sample and hold circuit when said first sample and hold circuit and said second sample and hold circuit for that said column of pixels are activated;
providing a single subtraction unit having a first input connected to said outputs of each of said first sample and hold circuits, a second input connected to said outputs of each of said second sample and hold circuits, and an output wherein the signal at said output of said subtraction unit is equal to the signal at said second input of said subtraction unit subtracted from the signal at said first input of said subtraction unit;
providing a buffer having an input connected to said output of said subtraction unit;
selecting one of said rows of pixels;
performing a first readout of said pixels in said selected row of pixels after an integration period and storing a first signal for each said pixel in said selected row of pixels in that said first sample and hold circuit associated with the same said column of pixels, wherein said first signal for each said pixel in said selected row of pixels is related to the potential of the photodiode in that said pixel at the time of said first readout;
resetting the potential of said photodiodes in said selected row of pixels after said first readout of said pixels in said selected row of pixels;
performing a second readout of said pixels in said selected row of pixels, immediately following said resetting the potential of said photodiodes in said selected row of pixels after said first readout, and storing a second signal for each said pixel in said selected row of pixels in that said second sample and hold circuit associated with the same said column of pixels, wherein said second signal for each said pixel in said selected row of pixels is related to the potential of the photodiode in that said pixel at the time of said second readout;
resetting the potential of said photodiodes in said selected row of pixels after said second readout of said pixels in said selected row of pixels to prepare for the next integration period; and
sequentially activating said first sample and hold circuit and said second sample and hold circuit for each of said M columns of pixels, thereby storing signals related to the amount of light incident on each of said photodiodes in said selected row of pixels during an integration period corrected for fixed pattern noise in said buffer.
5. The method of claim 4 wherein said subtraction unit is a digital subtraction unit and the signal at said output of said subtraction unit is produced in the digital domain.
6. The method of claim 4 wherein said subtraction unit is a differential video amplifier and the signal at said output of said subtraction unit is produced in the analog domain.
7. The method of claim 4 wherein each said first sample and hold circuit for each said column and each said second sample and hold circuit for each said column comprises:
a first FET having a source connected to said input of said first or second sample and hold circuit, a drain, and a gate;
a first capacitor having a first terminal connected to said drain of said first FET and a second terminal connected to ground potential;
a second capacitor having a first terminal connected to said drain of said first FET and a second terminal;
a second FET having a source connected to said second terminal of said second capacitor, a drain connected to ground potential, and a gate; and
a third FET having a source connected to said source of said second FET, a drain, and a gate, wherein said drain of said third FET of said first sample and hold circuit is connected to said output of said first sample and hold circuit, and said drain of said third FET of said second sample and hold circuit is connected to said output of said second sample and hold circuit.
8. The method of claim 7 wherein said storing a first signal for each said pixel in said selected row of pixels in that said first sample and hold circuit associated with the same said column of pixels is accomplished using control signals applied to said gates of said first FET and said second FET of that said first sample and hold circuit.
9. The method of claim 7 wherein said storing a second signal for each said pixel in said selected row of pixels in that said second sample and hold circuit associated with the same said column of pixels is accomplished using control signals applied to said gates of said first FET and said second FET of that said second sample and hold circuit.
10. The method of claim 7 wherein said sequentially activating said first sample and hold circuit and said second sample and hold circuit for each of said M columns of pixels is accomplished by applying sequenced select signals to said gate of said third FET in said first sample and hold circuit and said gate of said third FET in said second sample and hold circuit for each of said columns.
11. The method of claim 4 wherein said selecting one of said rows of pixels is accomplished using a row select FET for each said pixel.
12. A circuit for correcting for fixed pattern noise in an imager:
an imager having an array of N rows and M columns of pixels, wherein N and M are positive whole numbers and each pixel has a photodiode;
a first sample and hold circuit having an input and an output and a second sample and hold circuit having an input and an output for each of said columns of pixels, wherein a signal stored in said first sample and hold circuit is connected to said output of that said first sample and hold circuit and a signal stored in said second sample and hold circuit for the same said column of pixels is connected to said output of that said second sample and hold circuit when said first sample and hold circuit and said second sample and hold circuit for that said column of pixels are activated;
a single subtraction unit having a first input connected to said outputs of each of said first sample and hold circuits, a second input connected to said outputs of each of said second sample and hold circuits, and an output wherein the signal at said output of said subtraction unit is equal to the signal at said second input of said subtraction unit subtracted from the signal at said first input of said subtraction unit;
a buffer having an input connected to said output of said subtraction unit;
means for selecting one of said rows of pixels;
means for performing a first readout of said pixels in said selected row of pixels after an integration period and storing a first signal for each said pixel in said selected row of pixels in that said first sample and hold circuit associated with the same column of pixels, wherein said first signal for each said pixel in said selected row of pixels is related to the potential of the photodiode in that said pixel at the time of said first readout;
means for resetting the potential of said photodiodes in said selected row of pixels after said first readout of said pixels in said selected row of pixels;
means for performing a second readout of said pixels in said selected row of pixels, immediately following said resetting the potential of said photodiodes in said selected row of pixels after said first readout, and storing a second signal for each said pixel in said selected row of pixels in that said second sample and hold circuit associated with the same column of pixels, wherein said second signal for each said pixel in said selected row of pixels is related to the potential of the photodiode in that said pixel at the time of said second readout;
means for resetting the potential of said photodiodes in said selected row of pixels after said second readout of said pixels in said selected row of pixels, to prepare for the next integration period; and
means for sequentially activating said first sample and hold circuit and said second sample and hold circuit for each of said M columns of pixels, thereby storing signals related to the amount of light incident on each of said photodiodes in said selected row of pixels during an integration period corrected for fixed pattern noise in said buffer.
13. The circuit of claim 12 wherein said subtraction unit is a digital subtraction unit and the signal at said output of said subtraction unit is produced in the digital domain.
14. The circuit of claim 12 wherein said subtraction unit is a differential video amplifier and the signal at said output of said subtraction unit is produced in the analog domain.
15. The circuit of claim 12 wherein each said first sample and hold circuit for each said column and each said second sample and hold circuit for each said column comprises:
a first FET having a source connected to said input of said first or second sample and hold circuit, a drain, and a gate;
a first capacitor having a first terminal connected to said drain of said first FET and a second terminal connected to ground potential;
a second capacitor having a first terminal connected to said drain of said first FET and a second terminal;
a second FET having a source connected to said second terminal of said second capacitor, a drain connected to ground potential, and a gate; and
a third FET having a source connected to said source of said second FET, a drain, and a gate, wherein said drain of said third FET in said first sample and hold circuit is connected to said output of said first sample and hold circuit, and said drain of said third FET in said second sample and hold circuit is connected to said output of said second sample and hold circuit.
16. The circuit of claim 15 wherein said storing a first signal for each said pixel in said selected row of pixels in that said first sample and hold circuit associated with the same said column of pixels is accomplished using control signals applied to said gates of said first FET and said second FET of that said first sample and hold circuit.
17. The circuit of claim 15 wherein said storing a second signal for each said pixel in said selected row of pixels in that said second sample and hold circuit associated with the same said column of pixels is accomplished using control signals applied to said gates of said first FET and said second FET of that said second sample and hold circuit.
18. The circuit of claim 15 wherein said sequentially activating said sample and hold circuit pairs for each of said M columns of pixels is accomplished by applying sequenced select signals to said gate of said third FET in said first sample and hold circuit and said gate of said third FET in said second sample and hold circuit for each of said columns.
19. The circuit of claim 12 wherein said means for selecting one of said rows of pixels comprises a row select FET for each said pixel.