Nonvolatile semiconductor memory device and manufacturing method thereof

1. A nonvolatile semiconductor memory device, comprising:

a memory cell array having nonvolatile semiconductor memory elements arranged in a matrix in a word line direction and a bit line direction, each nonvolatile semiconductor memory element including a gate insulating film including a charge tapping layer formed on a substrate, a gate electrode formed on the gate insulating film, and a pair of diffusion layers formed in a surface layer of the substrate with the gate electrode interposed therebetween and functioning as a source or a drain;

first conductors for electrically connecting adjacent diffusion layers of adjacent nonvolatile semiconductor memory elements of the word line direction; and

bit lines for electrically connecting a plurality of the first conductors arranged in the bit line direction,

wherein ends of each gate electrode which respectively face a pair of diffusion layers of a corresponding nonvolatile semiconductor memory element are partially covered by the first conductor when viewed two-dimensionally.

2. The nonvolatile semiconductor memory device according to claim 1 , wherein the ends of each gate electrode which respectively face a pair of diffusion layers of a corresponding nonvolatile semiconductor memory element are completely covered by the first conductor when viewed two-dimensionally.

3. The nonvolatile semiconductor memory device according to claim 1 , wherein the first conductor is formed from polysilicon with a thickness of at least 50 mm.

4. The nonvolatile semiconductor memory device according to claim 1 , wherein the first conductor is formed from a metal wiring.

5. The nonvolatile semiconductor memory device according to claim 1 , wherein the first conductor includes a first contact and a first wiring, the first contact being formed from a metal and having its bottom end connecting to the diffusion layers, and the first wiring being formed from a metal and having its bottom surface connecting to a top end of the first contact.

6. The nonvolatile semiconductor memory device according to claim 1 , wherein the charge trapping layer has a multi-layer structure including a silicon oxide film and a silicon nitride film.

7. The nonvolatile semiconductor memory device according to claim 1 , wherein the charge trapping layer is formed from a silicon oxide film with fine silicon lumps dispersed therein.

8. A nonvolatile semiconductor memory device, comprising:

a memory cell array having nonvolatile semiconductor memory elements arranged in a matrix in a word line direction and a bit line direction, each nonvolatile semiconductor memory element including a gate insulating film including a charge tapping layer formed on a substrate, a gate electrode formed on the gate insulating film, and a pair of diffusion layers formed in a surface layer of the substrate with the gate electrode interposed therebetween and functioning as a source or a drain; and

bit lines for connecting every other pair of diffusion layers of a plurality of nonvolatile semiconductor memory elements arranged in the bit line direction, the bit lines including first conductors for electrically connecting adjacent diffusion layers of adjacent nonvolatile semiconductor memory elements of the word line direction, and second conductors for electrically connecting a plurality of first conductors arranged in the bit line direction, wherein

ends of each gate electrode which respectively face a pair of diffusion layers of a corresponding nonvolatile semiconductor memory element are partially covered by a corresponding first conductor when viewed two-dimensionally.

9. The nonvolatile semiconductor memory device according to claim 8 , wherein the ends of each gate electrode which respectively face a pair of diffusion layers of a corresponding nonvolatile semiconductor memory element are completely covered by a corresponding first conductor when viewed two-dimensionally.

10. The nonvolatile semiconductor memory device according to claim 8 , wherein the first conductors are formed from polysilicon with a thickness of at least 50 nm.

11. The nonvolatile semiconductor memory device according to claim 8 , wherein each of the first conductors is formed from a metal wiring.

12. The nonvolatile semiconductor memory device according to claim 8 , wherein each of the first conductors includes a first contact and a first wiring, the first contact being formed from a metal and having its bottom end connecting to the diffusion layers, and the first wiring being formed from a metal and having its bottom surface connecting to a top end of the first contact.

13. The nonvolatile semiconductor memory device according to claim 8 , wherein each of the second conductors includes a second contact and a second wiring, the second contact being formed from a metal and having its bottom end connecting to a top surface of a corresponding first conductor, and the second wiring being formed from a metal and having its bottom surface connecting to a top end of the second contact.

14. The nonvolatile semiconductor memory device according to claim 8 , wherein the ends of each gate electrode which respectively face a pair of diffusion layers of a corresponding nonvolatile semiconductor memory element are partially covered by a corresponding second conductor when viewed two-dimensionally.

15. The nonvolatile semiconductor memory device according to claim 8 , wherein the ends of each gate electrode which respectively face a pair of diffusion layers of a corresponding nonvolatile semiconductor memory element are completely covered by a corresponding second conductor when viewed two-dimensionally.

16. The nonvolatile semiconductor memory device according to claim 8 , wherein the charge trapping layer has a multi-layer structure including a silicon oxide film and a silicon nitride film.

17. The nonvolatile semiconductor memory device according to claim 8 , wherein the charge trapping layer is formed from a silicon oxide film with fine silicon lumps dispersed therein.

18. A nonvolatile semiconductor memory device, comprising:

a memory cell array having nonvolatile semiconductor memory elements arranged in a matrix in a word line direction and a bit line direction, each nonvolatile semiconductor memory element including a gate insulating film including a charge trapping layer formed on a substrate, a gate electrode formed on the gate insulating film, and a pair of diffusion layers formed in a surface layer of the substrate with the gate electrode interposed therebetween and functioning as a source or a drain; and

bit lines for connecting every other pair of diffusion layers of a plurality of nonvolatile semiconductor memory elements arranged in the bit line direction, the bit lines including first conductors for electrically connecting adjacent diffusion layers of adjacent nonvolatile semiconductor memory elements of the word line direction, and second conductors for electrically connecting a plurality of first conductors arranged in the bit line direction, wherein

ends of each gate electrode which respectively face a pair of diffusion layers of a corresponding nonvolatile semiconductor memory element are partially covered by a corresponding second conductor when viewed two-dimensionally.

19. The nonvolatile semiconductor memory device according to claim 18 , wherein the ends of each gate electrode which respectively face a pair of diffusion layers of a corresponding nonvolatile semiconductor memory element are completely covered by a corresponding second conductor when viewed two-dimensionally.

20. The nonvolatile semiconductor memory device according to claim 18 , wherein the charge tapping layer has a multi-layer structure including a silicon oxide film and a silicon nitride film.

21. The nonvolatile semiconductor memory device according to claim 18 , wherein the charge trapping layer is formed from a silicon oxide film with fine silicon lumps dispersed therein.