System and method for fully digital clock divider with non-integer divisor support
View Patent ↗A system and method that use a first clock to digitally generate a second clock, wherein the ratio of the frequency of the first clock to the frequency of the second clock is a non-integer. Circuitry may be used to ensure that the first clock, or input clock, has a frequency at least equal to the highest of the desired output frequencies. The input clock may be used to generate several output clocks with different frequencies. If one of the output clocks has the same frequency as the input clock, the circuitry can be bypassed. The different clocks may be used to drive parts of a system, each of which may require a different frequency.
1. A method for generating a second clock from a first clock, wherein the ratio of the frequency of the first clock to the frequency of the second clock is a non-integer, the method comprising:
generating cycles of the second clock, utilizing rising and falling edges of the first clock, wherein said cycles of the second clock have the duration of a first number of cycles of the first clock;
generating other cycles of the second clock, wherein the other cycles have the duration of a second number of cycles of the first clock;
calculating a first timing error between a time associated with a first edge of the first clock and a time for an edge at the frequency for the second clock;
calculating a second timing error between a time associated with a second edge of the first clock and the time for an edge at the frequency for the second clock;
generating an edge at the time of the first edge if the first timing error is less than the second timing error; and
generating an edge at the time of the second edge if the second timing error is less than the second timing error.
2. The method of claim 1 , wherein the absolute difference between the first number and the second number is one.
3. The method of claim 1 , wherein the second clock is used with video-related content.
4. The method of claim 1 , wherein the second clock is used for audio-related content.
5. The method of claim 1 , comprising:
breaking up a pattern of generated cycles and generated other cycles of the second clock.
6. The method of claim 5 , wherein said breaking up comprises using error diffusion techniques.
7. The method of claim 5 , wherein said breaking up comprises using dithering techniques.
8. The method of claim 1 , comprising:
adding a noise term to the second clock.
9. The method of claim 1 , wherein the second clock is used to drive audio components.
10. The method of claim 1 , wherein the second clock is used to drive video components.
11. The method of claim 1 , wherein the second clock is used in an audio/video ASIC decoder.
12. The method of claim 1 , wherein the method is used for audio/video synchronization.