Methods and apparatus for providing a software implemented cache memory
View Patent ↗Methods and apparatus provide a processor for operative connection to a main memory for storing data, the processor being operable to request at least some of the data for use; and a local memory in operative connection with the processor such that the data may be stored therein for use by the processor, the local memory not being a hardware cache memory, wherein the processor is operable to execute application program interface code that configures the local memory to include at least one software invoked cache memory area therein.
1. An apparatus, comprising:
at least one main processor coupled to a hardware implemented cache memory and coupled to a main memory, where the main processor obtains data from the main memory for storage in the cache memory;
a plurality of sub-processors, each coupled to the at least one main processor, each coupled to the main memory, and each obtaining at least some of the data from the main memory;
a respective local memory disposed on-chip with at least each sub-processor and connected therewith such that the data is stored for use by the at least each sub-processor, the local memory not being a hardware cache memory,
wherein at least each of the sub-processors executes application program interface code that configures the respective local memory thereof to include at least one software invoked cache memory area therein.
2. The apparatus of claim 1 , wherein the main processor, hardware cache memory, sub-processors and local memories are disposed on a common semiconductor chip.
3. The apparatus of claim 2 , wherein the main memory is also disposed on the common semiconductor chip.
4. The apparatus of claim 1 , wherein each of the sub-processors specifies at least one of the following parameters using the application program interface code:
a number of cache lines to include in the at least one software invoked cache memory area;
a size of the cache lines;
specific areas of the main memory from/to which to read/write the data;
a data size of the data that read from, or written to, the main memory in each such read/write cycle; and
a cache line replacement policy.
5. The apparatus of claim 1 , wherein the processor executes application program interface code that configures the local memory to include a plurality of distinct software invoked cache memory areas therein.
6. An apparatus, comprising:
at least one main processor coupled to a hardware implemented cache memory and coupled to a main memory, where the main processor obtains data from the main memory for storage in the cache memory;
a plurality of sub-processors, each coupled to the at least one main processor, each coupled to the main memory, and each obtaining at least some of the data from the main memory; and
a respective local memory disposed on-chip with at least each sub-processor and connected therewith such that the data is stored for use by the at least each sub-processor, the local memory not being a hardware cache memory.
7. The apparatus of claim 6 , wherein the processors and associated local memories are disposed on a common semiconductor substrate.
8. The apparatus of claim 6 , further comprising the shared memory coupled to the processors over a bus.
9. The apparatus of claim 8 , wherein the processors, associated local memories, and the shared memory are disposed on a common semiconductor substrate.