Enhanced nanowire-crossbar latch array
View Patent ↗Various embodiments of the present invention are directed to a signal-storing nanowire-crossbar latch array. In one embodiment, the signal-storing nanowire-crossbar latch array is fabricated from three signal lines, including an enable line and two control lines, that cross and intersect with a number of signal wires. Signals are stored in the nanowire-crossbar latch array, and output from the nanowire-crossbar latch array, by applying an input signal to each signal wire and applying selected voltages and voltage pulses to the control lines. In alternate embodiments, a second enable line that crosses and interconnects with each signal wire is added to the nanowire-crossbar latch array.
1. A nanowire-crossbar latch array for storing input signals, the nanowire-crossbar latch array comprising:
a number of signal wires;
a first enable line crossing each signal wire, the first enable line interconnected to each signal wire by one of a field-effect-transistor nanowire junction and a high resistance nanowire junction, the first enable line controlling input-signal transmission in any of the signal wires to which the first enable line is interconnected by a field-effect transistor;
a second enable line crossing each signal wire, the second enable line interconnected to each signal wire, the second enable line interconnected to a given signal wire by a field-effect-transistor nanowire junction when the first enable line is connected to the given signal wire by a high resistance nanowire junction, the second enable line interconnected to a given signal wire by a high resistance nanowire junction when the first enable line is connected to the given signal wire by a field-effect transistor;
a first control line crossing each signal wire, the first control line interconnected to each signal wire by an asymmetric switch of a first type; and
a second control line crossing each signal wire, the second control line interconnected to each signal wire by an asymmetric switch of a second type.
2. The nanowire-crossbar latch array of claim 1 wherein the nanowire junctions that interconnect the first enable line with each signal wire are field-effect transistors and the nanowire junctions that interconnect the second enable line with each signal wire are each one of:
a field-effect transistor; and
a high resistance nanowire junction.
3. A nanoscale circuit comprising:
a nanoscale logic array; and
a number of nanowire-crossbar latch arrays interconnected with the nanoscale logic array, each nanowire-crossbar latch array including
a number of signal wires,
a first enable line crossing each signal wire, the first enable line interconnected to each signal wire by a nanowire junction, the first enable line controlling input-signal transmission in any of the signal wires to which the first enable line is interconnected by a field-effect transistor nanowire junction,
a second enable line crossing each signal wire, the second enable line interconnected to each signal wire by a nanowire junction,
a first control line crossing each signal wire, the first control line interconnected to each signal wire by a signal-storing nanowire junction, and
a second control line crossing each signal wire, the second control line interconnected to each signal wire by a signal-storing nanowire junction.
4. The nanoscale circuit of claim 3 wherein the nanowire junctions that interconnect the first enable line with each signal wire are field-effect transistors and the nanowire junctions that interconnect the second enable line with each signal wire are each one of:
a field-effect transistor; and
a high resistance nanowire junction.
5. A method for storing information in, and outputting stored information from, a nanoscale circuit, the method comprising:
providing a nanowire-crossbar latch array having a number of signal wires that transmit input and output signals, a field-effect transistor or a high resistance nanowire junction at each nanowire junction interconnecting each signal wire and a first enable line, a field-effect transistor or a high resistance nanowire junction at each nanowire junction interconnecting each signal wire and a second enable line, a first type of asymmetric switch at each nanowire junction interconnecting each signal wire and a first control line, and a second type of asymmetric switch at each nanowire junction interconnecting each signal wire and a second control line;
storing a signal by
applying the signal as input to each signal wire,
applying voltage V enable to the first enable line,
applying an unconditional-open-voltage pulse to the first and second control lines, and
applying a conditional-close voltage pulse to the first and second control lines; and
outputting stored signals by
applying voltage V disable to the first enable line, and
applying a strong 0 voltage to the first control line and a strong 1 voltage to the second control line.
6. The method of claim 5 further comprising applying voltage V disable to the second enable line.
7. The method of claim 5 further comprising outputting inverted stored signals by:
applying voltage V disable to the first enable line; and
applying a strong 1 voltage to the first control line and a strong 0 voltage to the second control line.
8. The method of claim 7 wherein the nanowire-crossbar latch array further comprises a field-effect transistor or a high resistance nanowire junction interconnecting each signal wire and a second enable line.
9. The method of claim 8 further comprising applying voltage V disable to the second enable line.
10. A method for storing information in a nanoscale circuit, the method comprising:
providing a nanowire-crossbar latch array having a number of signal wires that transmit input and output signals, a first control line interconnected to each signal wire by an asymmetric switch nanowire junction, a second control line interconnected to each signal wire by an asymmetric switch nanowire junction, a first enable line interconnected to each signal wire by one of, a field-effect transistor or a high resistance nanowire junction, and a second enable line interconnected to each signal wire by one of, a field-effect transistor or a high resistance nanowire junction, when the interconnection between a signal wire and one of the two enable lines is a field-effect transistor, the interconnection between the signal wire and the other of the two enable lines is a high resistance nanowire junction;
applying an input signal to each signal wire;
applying voltage V enable to the field-effect-transistor-interconnected enable line;
applying an unconditional-open-voltage pulse to the first and second control lines; and
applying a conditional-close voltage pulse to the first and second control lines.
11. The method of claim 10 further comprising outputting stored signals by:
applying voltage V disable to the field-effect-transistor-interconnected enable line; and
applying a strong 0 voltage to the first control line and a strong 1 voltage to the second control line.
12. The method of claim 10 further comprising outputting inverted stored signals by:
applying voltage V disable to the field-effect-transistor-interconnected enable line; and
applying a strong 1 voltage to the first control line and a strong 0 voltage to the second control line.