Liquid crystal display device and fabricating method thereof
View Patent ↗A thin film transistor substrate and a fabricating method simplify a process and enlarge a capacitance value of a storage capacitor without any reduction of aperture ratio. A transparent first conductive layer and an opaque second conductive layer of a double-layer structured gate line are formed having a step coverage. A pixel electrode is provided on the gate insulating film within a pixel hole of said pixel area passing through the passivation film to be connected to the thin film transistor. A storage capacitor overlaps with the pixel electrode with having the gate insulating film therebetween and has a lower storage electrode protruded from the first conductive layer.
1. A liquid crystal display device, comprising:
a double-layer structure of a gate line, the double layer having a first transparent conductive layer and a second opaque conductive layer and having a step coverage;
a data line crossing to the gate line to define a pixel region;
a gate insulating film between the gate line and the data line;
a thin film transistor connected to the gate line and the data line;
a semiconductor layer defining a channel of the thin film transistor and overlapping with the data line;
a passivation film covering the data line and the thin film transistor;
a pixel electrode directly formed on the gate insulating film which is exposed by a pixel hole in the pixel region; and
a storage capacitor overlapping with the pixel electrode having the gate insulating film therebetween and having a lower storage electrode extended from the first transparent conductive layer.
2. The device as claimed in claim 1 , further comprising:
a gate pad including a lower gate pad electrode having the double-layer structure connected to the gate line, and an upper gate pad electrode within a contact hole passing through the gate insulating film and the passivation film.
3. The device as claimed in claim 1 , further comprising:
a data pad including a lower data pad electrode connected to the data line, and an upper data pad electrode within a contact hole passing through the passivation film,
wherein the semiconductor layer overlaps with the lower data pad electrode.
4. The device substrate as claimed in claim 3 , wherein the upper data pad electrode is substantially laterally connected to the lower data pad electrode through the contact hole.
5. The device as claimed in claim 1 , wherein the pixel electrode is substantially laterally connected to the drain electrode through the pixel hole.
6. The device as claimed in claim 1 , wherein the gate electrode is connected to the gate line.