Liquid crystal display device and fabricating method thereof

1. A method of fabricating a liquid crystal display device, comprising:

forming a gate pattern including a gate line, a gate electrode and a lower storage electrode on a substrate using a first mask, the gate line and the gate electrode being formed of a double-layer having a transparent conductive layer, and the lower storage electrode being formed of the transparent conductive layer;

forming a gate insulating film on the gate pattern;

forming a semiconductor pattern and a source/drain pattern having a data line and source and drain electrodes on the gate insulating film using a second mask, the data line defining a pixel region with the gate line;

forming a protective film on the source/drain pattern, and forming a contact hole exposing the drain electrode using a third mask; and

forming a pixel electrode connected to the drain electrode via the contact hole on the protective film and overlapping with the lower storage electrode using a fourth mask,

wherein the portion of the gate insulating film over the lower storage electrode is exposed by using the second mask, and a portion of the protective film is formed on and in contact with said portion of the gate insulating film; and

wherein the portion of the pixel electrode overlapping with the lower storage electrode forms an upper storage electrode.

2. The method of claim 1 , wherein forming the gate pattern includes:

forming a first conductive layer as the transparent layer and a second conductive layer on the substrate;

forming first and second photo-resist patterns having a different thickness on the second conductive layer by photolithography using the first mask;

forming the gate line, the gate electrode and the lower storage electrode by patterning the first and second conductive layers by etching using the first and second photo-resist patterns;

removing the second conductive layer on the lower storage electrode by etching using the first photo-resist pattern; and

removing the first photo-resist pattern.

3. The method of claim 2 , further comprising thinning the first photo-resist pattern and removing the second photo-resist pattern by ashing after forming the gate line and the gate electrode.

4. The method of claim 1 , wherein the lower storage electrode protrudes from the transparent conductive layer of the gate line toward the pixel region.

5. The method of claim 2 , wherein forming the gate pattern further includes forming a common line crossing the pixel electrode and the data line, the common line being formed of a transparent conductive layer having the lower storage electrode.

6. The method of claim 1 , wherein the forming the gate pattern includes forming a common line crossing the pixel electrode and the data line, the common line being double layered,

wherein the lower storage electrode protrudes from a first conductive layer of the common line toward the pixel region.

7. The method of claim 1 , wherein the forming the gate pattern includes a redundancy line independently overlapping the data line between the gate lines.

8. The method of claim 7 , wherein the redundancy line is formed of one of a first conductive layer and double-layer structure.

9. The method of claim 1 , wherein forming the gate pattern includes forming a light-sheilding pattern protruded from a second conductive layer of the gate line to overlap both sides of the pixel electrode.

10. The method of claim 9 , wherein the light-sheilding pattern overlaps the lower storage electrode.

11. The method of claim 1 , further comprising:

forming a lower gate pad electrode having a double-layer, the lower gate pad electrode being connected to the gate lane;

forming a second contact hole passing through the gate insulating film and the protective film; and

forming an upper gate pad electrode connected to the lower gate pad electrode via the second contact hole.

12. The method of claim 11 , further comprising:

forming a lower data pad electrode connected to the data line;

forming a third contact hole passing through the protective film; and

forming an upper data pad electrode connected to the lower data pad electrode via the third hole.

13. The method of claim 1 , wherein forming the gate pattern further includes forming a third conductive layer along with a second conductive layer.

14. The method of claim 1 , wherein first and second conductive layers of the double-layer have a constant step coverage.

15. The method of claim 1 , wherein the first mask is a half tone mask.

16. The method of claim 1 , wherein the second mask is a diffractive exposure mask.

17. The method of claim 1 , wherein the semiconductor pattern forms a part of the date line.