Method of increasing DDR memory bandwidth in DDR SDRAM modules
View Patent ↗The present invention provides a method of increasing DDR memory bandwidth in DDR SDRAM modules. DDR memory has an inherent feature called the Variable Early Read command, where the read command is issued one CAS latency before the termination of an ongoing data burst By using the Variable Early Read command the effect of the CAS latency is minimized in terms of the effect on bandwidth. The enhanced bandwidth technology achieved with this invention optimizes the remaining two access latencies (t RP and t RCD ) for optimal bandwidth. These optimizations in the SPD allow for much better bandwidth in real world applications.
1. A method for optimizing data transfer between memory modules and at least one memory controller using at least one memory module, the at least one memory module containing firmware and a plurality of double date rate (DDR) integrated circuit chips, each of said integrated circuit chips supporting page mode access, a bank activate command having associated therewith a row access strobe (RAS)-to-column access strobe (CAS) delay, a read command having associated therewith a CAS latency, and a precharge command having associated therewith a precharge latency, the method comprising the step of:
setting the firmware for high-speed access including: setting the CAS latency to a CAS latency value that is greater than a minimum CAS latency value supported by said integrated circuit chips at a selected frequency; and
setting at least one of the RAS-to-CAS delay and the precharge latency to a RAS-to-CAS delay value and a precharge latency value, respectively, lower than the set CAS latency value to minimize access times of consecutive accesses in which a subsequent access is out-of-page from an immediately previous access; using said precharge command to close a first page where the immediately previous access occurred; and using said bank activate command to open a second page different than the first page to access data within said second page using the read command.
2. The method according to claim 1 where the integrated circuit chips used on the memory modules conform to the DDR1 standard.
3. The method according to claim 1 where the integrated circuit chips used on the memory modules conform to the DDR2 standard.
4. The method according to claim 1 where the integrated circuit chips used on the memory modules conform to the DDR3 standard.
5. The method according to claim 4 , wherein at least one memory module conforms to a small form factor.
6. The method according to claim 4 wherein both the RAS-to-CAS delay value and the precharge latency value are set lower than the set CAS latency value.
7. The method according to claim 1 , wherein the at least one memory module conforms to a small form factor.
8. The method according to claim 1 , wherein the at least one memory module conforms to a fully buffered DIMM.
9. The method of claim 1 where the precharge command is generated by the integrated circuit chips used on the memory modules.
10. The method according to claim 1 wherein both the RAS-to-CAS delay value and the precharge latency value are set lower than the set CAS latency value.
11. The method according to claim 1 wherein the steps of setting result in reduced missed read accesses during the steps of using.
12. A memory apparatus comprising: a memory controller; at least one memory module that communicates with the memory controller and contains a plurality of double date rate (DDR) integrated circuit chips, each of said integrated circuit chips supporting page mode access, a bank activate command having associated therewith a row access strobe (RAS)-to-column access strobe (CAS) delay, a read command having associated therewith a CAS latency, and a precharge command having associated therewith a precharge latency; and firmware for high speed access, wherein the firmware for high-speed access includes: a CAS latency value for setting the CAS latency that is greater than a minimum CAS latency value supported by said integrated circuit chips at a selected frequency; and
a RAS-to-CAS delay value and a precharge latency value for setting the RAS to CAS delay and the precharge latency, respectively, at least one of the RAS-to-CAS delay value and the precharge latency value being set lower than the set CAS latency value to minimize access times of consecutive accesses in which a subsequent access is out-of-page from an immediately previous access, such that the firmware specifies minimal numbers of penalty cycles from: said precharge command until a first page where the immediately previous access occurred is closed; and said bank activate command until a second page different than the first page is opened to access data within said second page using the read command.
13. The apparatus according to claim 12 wherein the memory controller is integrated with the at least one memory module.
14. The apparatus according to claim 12 wherein the memory controller is separate from the at least one memory module.
15. The apparatus according to claim 12 wherein the firmware is integrated with the at least one memory module.
16. The apparatus according to claim 12 wherein the firmware is separate from the at least one memory module.
17. The apparatus according to claim 12 wherein the memory controller is a plurality of memory controllers, each of which communicates with the at least one memory module.
18. The apparatus according to claim 12 where the integrated circuit chips used on the memory modules conform to one of DDR1, DDR2, and DDR3 standards.
19. The apparatus according to claim 18 where the at least one memory module conforms to a small form factor.
20. The apparatus according to claim 18 wherein both the RAS-to-CAS delay value and the precharge latency value are set lower than the set CAS latency value.
21. The apparatus according to claim 12 where the at least one memory module conforms to a small form factor.
22. The apparatus according to claim 12 where the at least one memory module conforms to a fully buffered DIMM.
23. The apparatus of claim 12 where the precharge command is generated by the integrated circuit chips used on the memory module.
24. The apparatus according to claim 12 wherein both the RAS-to-CAS delay value and the precharge latency value are set lower than the set CAS latency value.
25. The apparatus according to claim 12 wherein the CAS latency value, RAS-to-CAS delay value and the precharge latency value settings result in reduced missed read accesses.