System for controlling context switch of deferred requests using counter and flag setting of thread accessing shared resource or entering code region
View Patent ↗In an embodiment of the invention, a method for a memory-mapped lazy preemption control, the method includes: incrementing a counter value if an operating system attempts to involuntarily context switch out a thread and fails to context switch out the thread because the thread has a flag set; checking a counter value to determine a degree of abusiveness of a thread; and based upon the degree of abusiveness, determining if a voluntary contact switch out should be performed or should not be performed on the thread.
1. A method comprising:
receiving a first operating system call from a thread, the operating system call including a location identifier for a flag, the flag being set to a first state by the thread when the thread is at least one of executing a code region or is accessing a shared resource;
deferring a first request to context switch the thread when the flag is in the first state;
incrementing a counter value with an operating system when the first request is deferred;
deferring a second request to context switch the thread when the flag is in the first state;
incrementing the counter value with the operating system when the second request is deferred;
receiving a second operating system call from the thread when the thread detects that the counter value exceeds a threshold, the second operating system call including a request to context switch the thread; and
context switching the thread in response to the second operating system call.
2. The method of claim 1 , further comprising allocating a first memory area to the flag.
3. The method of claim 1 , wherein the flag is memory mapped into an application address area.
4. The method of claim 1 , wherein the counter value is memory mapped into an application address area.
5. The method of claim 1 , wherein the location identifier represents an address of a memory area that stores the flag.
6. The method of claim 1 , wherein the flag is set to a second state by the thread when the thread is not executing the code region and is not accessing the shared resource.
7. The method of claim 1 , further comprising accessing the flag via the location identifier to determine whether to defer to the first request.
8. The method of claim 1 , further comprising decrementing the counter value after context switching the thread, wherein the operating system decrements the counter value.
9. The method of claim 1 , wherein the flag is writable by the thread and readable, but not writable, by the operating system.
10. The method of claim 1 , wherein the counter value is writable by the operating system and readable, but not writable, by the thread.
11. A method comprising:
sending a first operating system call from a thread to an operating system, the operating system call including a location identifier for a flag;
setting the flag within the thread to a first state when the thread is at least one of entering a code region or is accessing a shared resource;
comparing within the thread a counter value to a threshold to determine whether to context switch the thread, wherein the operating system increments the counter to represent a number of deferred requests to context switch the thread when the flag is set to the first state; and
sending a second operating system call from the thread to the operating system when the thread detects that the counter value exceeds the threshold, the second operating system call including a request to context switch the thread, wherein the operating system context switches the thread in response to the second operating system call.
12. The method of claim 11 , further comprising allocating a first memory area for the flag.
13. The method of claim 11 , wherein the flag is memory mapped into an application address area.
14. The method of claim 11 , wherein the counter value is memory mapped into an application address area.
15. The method of claim 11 , further comprising setting the flag to a second state with the thread when the thread is not executing the code region and is not accessing the shared resource.
16. The method of claim 11 , further comprising yielding a processor.
17. The method of claim 11 , wherein the location identifier represents an address of a memory area that stores the flag.
18. The method of claim 11 , further comprising continuing execution of the thread when the thread determines that the counter value is less than the threshold.
19. The method of claim 11 , wherein the flag is writable by the thread and readable, but not writable, by the operating system.
20. The method of claim 11 , wherein the counter value is writable by the operating system and readable, but not writable, by the thread.
21. A tangible article of manufacture storing machine-readable instructions that, when executed, cause a machine to:
send a first operating system call from a thread to an operating system, the operating system call including a location identifier for a flag;
set the flag with the thread to a first state when the thread is at least one of entering a code region or is accessing a shared resource;
compare with the thread a counter value to a threshold to determine whether to context switch the thread, wherein the operating system increments the counter to represent a number of deferred requests to context switch the thread when the flag is set to the first state; and
send a second operating system call from the thread to the operating system when the thread detects that the counter value exceeds the threshold, the second operating system call including a request to context switch the thread, wherein the operating system context switches the thread in response to the second operating system call.
22. The article of manufacture of claim 21 , wherein the location identifier represents an address of a memory area that stores the flag.
23. The article of manufacture of claim 21 , wherein the machine-readable instructions, when executed, cause the machine to continue execution of the thread when the thread determines that the counter value is less than the threshold.
24. The article of manufacture of claim 21 , wherein the flag is writable by the thread and readable, but not writable, by the operating system.
25. The article of manufacture of claim 21 , wherein the counter value is writable by the operating system and readable, but not writable, by the thread.
26. The article of manufacture of claim 21 , wherein the machine-readable instructions, when executed, cause the machine to allocate a first memory area for the flag.
27. The article of manufacture of claim 21 , wherein the machine-readable instructions, when executed, cause the machine to memory map the flag into an application address area.
28. The article of manufacture of claim 21 , wherein the machine-readable instructions, when executed, cause the machine to memory map the counter value into an application address area.
29. The article of manufacture of claim 21 , wherein the machine-readable instructions, when executed, cause the machine to set the flag to a second state when the thread is not executing the code region and is not accessing the shared resource.
30. The article of manufacture of claim 21 , wherein the machine-readable instructions, when executed, cause the machine to yield a processor.
31. A tangible article of manufacture storing machine-readable instructions that, when executed, cause a machine to:
receive a first operating system call from a thread, the operating system call including a location identifier for a flag, the flag being set to a first state by the thread when the thread is at least one of executing a code region or is accessing a shared resource;
defer a first request to context switch the thread when the flag is in the first state;
increment a counter value by an operating system when the first request is deferred;
defer a second request to context switch the thread when the flag is in the first state;
increment the counter value by the operating system when the second request is deferred;
receive a second operating system call from the thread when the thread detects that the counter value exceeds a threshold, the second operating system call including a request to context switch the thread; and
context switch the thread in response to the second operating system call.
32. The article of manufacture of claim 31 , wherein the machine-readable instructions, when executed, cause the machine to allocate a first memory area for the flag.
33. The article of manufacture of claim 31 , wherein the machine-readable instructions, when executed, cause the machine to memory map the flag into an application address area.
34. The article of manufacture of claim 31 , wherein the machine-readable instructions, when executed, cause the machine to memory map the counter value into an application address area.
35. The article of manufacture of claim 31 , wherein the location identifier represents an address of a memory area that stores the flag.
36. The article of manufacture of claim 31 , wherein the flag is set to a second state by the thread when the thread is not executing the code region and is not accessing the shared resource.
37. The article of manufacture of claim 31 , wherein the machine-readable instructions, when executed, cause the machine to access the flag via the location identifier to determine whether to defer to the first request.
38. The article of manufacture of claim 31 , wherein the machine-readable instructions, when executed, cause the machine to decrement the counter value after context switching the thread, wherein the operating system decrements the counter value.
39. The article of manufacture of claim 31 , wherein the flag is writable by the thread and readable, but not writable, by the operating system.
40. The article of manufacture of claim 31 , wherein the counter value is writable by the operating system and readable, but not writable, by the thread.