Liquid crystal display device having GOLDD type TFT and LDD type TFT and method of making same

1. A liquid crystal display device, comprising:

an image display unit having unit pixels arranged thereon in a matrix;

a driving circuit unit applying a driving signal to the image display unit, wherein the driving circuit unit includes,

a gate driver for supplying gate signals to gate lines of the display unit;

a data driver for applying data signals to data lines;

an output buffer block within the gate driver;

a level shifter in the driving circuit unit;

a timing controller for generating control signals to be supplied to the gate driver and the data driver by receiving signals inputted from an exterior;

a DC-DC (Direct Current-Direct Current) converter for converting a DC voltage input from the exterior into a DC voltage required for driving a liquid crystal display panel;

a DA (Digital-to-Analog) converter for converting a digital signal inputted from the exterior into an analog signal;

a gamma voltage generator;

a shift resister for storing the control signals inputted from the timing controller; and

a common voltage driver for adjusting a common voltage;

a first CMOS by paring a LDD TFT with a PMOS; and

a second CMOS by pairing a GOLDD TFT with the PMOS,

wherein the output buffer block within the gate driver, the level shifter in the driving circuit unit, a pixel switching TFT in the display unit, and all other devices driven by high voltage more than 10V are formed by the second CMOS adopting the GOLDD TFT, and

wherein the timing controller, the shift resistor within the data driver, the DC-DC converter, the common voltage driver, and all other devices driven by a low voltage less than 10V are formed by the first CMOS adopting the LDD TFT.

2. The device of claim 1 , wherein:

the data driver includes:

the shift resister for storing the control signal inputted from the timing controller;

the digital-to-analog converter (DAC) for converting a control signal inputted from the shift resister into an analog signal for the image display unit; and

a first output buffer block for applying a control signal inputted from the DAC to the data lines; and

the gate driver includes:

the shift resister;

the level shifter for carrying the control signal inputted from the shift resister to a specific level; and

a second output buffer block for applying a control signal inputted from the level shifter to the gate lines of the image display unit.

3. The device of claim 1 , wherein the LDD TFT, the GOLDD TFT, and the PMOS comprise:

first, second and third active layers on a transparent substrate; a gate insulating layer over the active layers;

first, second and third gate electrodes on the gate insulating layer, wherein each of the gate electrodes is formed at the first, second and third active layers, respectively;

a first LDD region formed in the first active layer at sides of the first gate electrode, and a second LDD region formed in the second active layer under the second gate electrode; and

source and drain regions in the first, second and third active layer at sides of the first, second and third gate electrodes.

4. The device of claim 1 , wherein the LDD TFT comprises:

a first active layer on a transparent substrate;

a gate insulating layer over the first active layer;

the first gate electrode on the gate insulating layer;

a first LDD region formed in the first active layer, wherein the first LDD region is formed in the first active layer at sides of the first gate electrode; and

source and drain regions in the first active layer at the sides of the first gate electrode.

5. The device of claim 1 , wherein the GOLDD TFT comprises:

a second active layer on a transparent substrate;

a gate insulating layer over the second active layer;

the second gate electrode on the gate insulating layer; a second LDD region formed in the second active layer, wherein the second LDD region is formed in the second active layer under the second gate electrode; and

source and drain regions in the second active layer at sides of the second gate electrode.

6. The device of claim 1 , wherein the PMOS comprises:

a third active layer on a transparent substrate;

a gate insulating layer over the third active layer;

the third gate electrode on the gate insulating layer; and

source and drain regions in the third active layer at sides of the third gate electrode.