Method and system to implement an improved floating point adder with integrated adding and rounding
View Patent ↗Systems and methods to implement an improved floating point adder are presented. The adder integrates adding and rounding. According to an exemplary method, of adding two floating point numbers together, a first mantissa, a second mantissa, and an input bit are added together to produce a third mantissa. The third mantissa is normalized to produce a final mantissa. The third mantissa and the final mantissa are correctly rounded as a result of the act of adding, so that the final mantissa does not require processing by a follow on rounding stage.
1. A floating point number adder system to add a first floating point number to a second floating point number, the system comprising:
an adder that performs an add operation to add a first mantissa associated with the first floating point number, a second mantissa associated with the second floating point number, and an input bit to produce a third mantissa and an output bit;
a round control logic circuit that produces round control data derived from the first mantissa and the second mantissa;
a carry logic circuit, coupled to the output bit and the round control logic circuit, that generates the input bit; and
a normalizer stage coupled to the adder and adapted to normalize the third mantissa and produce a final mantissa;
wherein the third mantissa and the final mantissa are correctly rounded as a result of the add operation performed by the adder.
2. The system according to claim 1 , wherein the round control logic circuit produces the round control data based on a sign control bit associated with the first floating point number and the second floating point number.
3. The system according to claim 1 , wherein the normalizer stage receives a control bit derived from the round control data.
4. The system according to claim 1 , wherein the carry logic circuit receives a plurality of carry logic signals.
5. The system according to claim 1 , wherein a less significant bit of the third mantissa depends on a more significant bit of the second mantissa.
6. The system according to claim 1 , wherein the first mantissa is aligned with the second mantissa prior to adding.
7. The system according to claim 1 , wherein the system shifts a larger or equal floating point number of the first floating point number and the second floating point number by one position to produce the first mantissa, prior to adding, if both of the first and second floating point numbers are positive.
8. The system according to claim 1 , wherein the system shifts in a number of zeroes into a smaller or equal floating point number of the first floating point number and the second floating point number to produce a series of control variables and a fourth mantissa having digits, prior to the adding, if both of the first and second floating point numbers are positive, and complements each digit of the fourth mantissa to produce the second mantissa.
9. A digital floating point adder comprising:
an unpack stage having a first input for a binary representation of a first floating point number, a second input for a binary representation of a second floating point number, a first output for a first mantissa associated with the first floating point number, and a second output for a second mantissa associated with the second floating point number;
a round control logic circuit having an input coupled to the first and second outputs of the unpack stage, and an output for round control data generated from the input of the round control circuit;
a binary adder having a first input coupled to the first output of the unpack stage, a second input coupled to the second output of the unpack stage, and a third input for receiving an input bit, the adder further having a first output for the sum of the first, second, and third inputs, and a second output for an output bit;
a carry logic circuit having a first input coupled to the output of the round control logic, a second input coupled to the second output of the binary adder, and an output coupled to the third input of the binary adder.
10. A digital floating point adder according to claim 9 , wherein the output of the round control logic circuit includes a GEN output and a PROP output, and wherein the output of the carry logic circuit is True if and only if either GEN is True, or both PROP and the output bit of the binary adder are true.
11. A digital floating point adder according to claim 10 , wherein the output bit of the binary adder is a carry bit selected from the group consisting of the most significant carry bit and the second most significant carry bit.
12. A digital floating point adder according to claim 9 , further comprising a normalizer stage having an input coupled to the first output of the binary adder, the normalizer stage being operative to left-shift the first output of the binary adder to remove leading zeros and to generate a normalized mantissa, the normalizer stage having an output operative to remove the least significant bit of the normalized mantissa to generate a final mantissa;
wherein the round control logic is operative to generate round control data such that the final mantissa is correctly rounded.
13. A digital floating point adder according to claim 12 , wherein the normalizer stage is not coupled to a rounding stage.
14. A digital floating point adder according to claim 9 , further comprising a complement stage, wherein the input of the round control logic circuit is coupled to the second output of the unpack stage through the complement stage.