Automatic fault-testing of logic blocks using internal at-speed logic-BIST
View Patent ↗System and method for automatic fault-testing of a logic block and the interfaces of macros with logic gates inside a chip, using an at-speed logic-BIST internal to the chip. Following an initialization of internal storage elements, a set of test signals are generated and processed by the logic block. The output of the logic block is accumulated into a signature and compared to a reference signature to detect faults. Testing can be performed on an ATE (Automatic Test Equipment) using a simple test vector, or can be performed by a field engineer on the actual board comprising the chip.
1. A semiconductor device, comprising:
a logic block having a set of flip-flops and memories connected to a clock signal and a reset signal;
a pattern generator for generating a set of test signals for processing by the logic block;
a signature accumulator for producing a test signature based on a set of outputs produced by the logic block upon processing the test signals; and
a built-in self-test (logic-BIST) circuit for initializing the flip-flops and memories by writing to the flip-flops and memories known values of the reset signal during a same number of clock cycles and initiating testing of the logic block;
wherein initializing the flip-flops and memories causes them to simultaneously store the known values despite timing variations or propagation delays of the reset signal across the flip-flops and memories.
2. A semiconductor device as recited in claim 1 , the logic-BIST circuit for initializing the flip-flops and memories by performing the following sequence:
(a) gating the clock signal;
(b) activating the reset signal;
(c) resuming the clock signal while holding the reset signal active;
(d) gating the clock signal again; and
(e) deactivating the reset signal.
3. A semiconductor device as recited in claim 2 , the logic-BIST circuit further for comparing the test signature to a reference signature, the reference signature representing the result of fault-free processing of the set of test signals by the logic block.
4. A semiconductor device as recited in claim 3 , wherein the reference signature is computed by simulating fault-free operation of the logic block on the set of test signals.
5. A semiconductor device as recited in claim 2 , wherein the logic block comprises a video decoder logic block for decoding video signals, and the pattern generator generates the set of test signals according to a standard selected from the group consisting of NTSC, PAL, SECAM, composite video, S-video, and component video or according to non-standard inputs in order to increase fault coverage.
6. A semiconductor device as recited in claim 2 , wherein the signature accumulator comprises a cyclic redundancy check (CRC) for producing the test signature by incrementally compressing the set of outputs produced by the logic block.
7. A semiconductor device as recited in claim 2 , wherein the logic-BIST circuit determines the times at which the signature accumulator reads the set of outputs produced by the logic block.
8. A semiconductor device as recited in claim 1 , the logic block having a memory element, the logic-BIST further for initializing the memory element by flushing it with known values.
9. A method for testing a logic block having a set of flip-flops connected to a clock signal and a reset signal, the method comprising:
initializing the set of flip-flops by writing to the flip-flops known values of the reset signal during a same number of clock cycles;
generating a set of test signals for processing by the logic block; and
producing a test signature based on a set of outputs produced by the logic block upon processing the test signals;
wherein initializing the set of flip-flops causes them to simultaneously store the known values despite timing variations or propagation delays of the reset signal across the set of flip-flops.
10. A method as recited in claim 9 , wherein initializing the set of flip-flops comprises the following sequence:
(a) gating the clock signal;
(b) activating the reset signal;
(c) resuming the clock signal while holding the reset signal active;
(d) gating the clock signal again; and
(e) deactivating the reset signal.
11. A method as recited in claim 10 , further comprising:
comparing the test signature to a reference signature, the reference signature representing the result of fault-free processing of the set of test signals by the logic block.
12. A method as recited in claim 11 , wherein the reference signature is computed by simulating fault-free operation of the logic block on the set of test signals.
13. A method as recited in claim 10 , wherein the logic block comprises a video decoder logic block for decoding video signals, and the set of test signals are generated according to a standard selected from the group consisting of NTSC, PAL, SECAM, composite video, S-video, and component video.
14. A method as recited in claim 10 , wherein producing the test signature comprises incremental compression of the set of outputs produced by the logic block.
15. A method as recited in claim 14 , wherein incremental compression of the set of outputs comprises using a linear feedback shift register (LFSR).
16. A method as recited in claim 10 , wherein generating a set of test signals is performed by a pattern generator residing in the same semiconductor device as the logic block.
17. A method as recited in claim 10 , wherein producing a test signature is performed by a signature accumulator residing in the same semiconductor device as the logic block.
18. A method as recited in claim 10 , wherein initializing the set of flip-flops is performed by a built-in self test circuit (logic-BIST) residing in the same semiconductor device as the logic block.
19. A method as recited in claim 9 , the logic block having a memory element, further comprising:
initializing the memory element by flushing it with known values.
20. A method as recited in claim 19 , wherein flushing the memory element comprises the following sequence:
(a) gating the clock signal;
(b) activating the reset signal;
(c) resuming the clock signal while holding the reset signal active;
(d) gating the clock signal again; and
(e) deactivating the reset signal.
21. A method for testing a semiconductor device having a logic block, a pattern generator, a signature accumulator and a built-in self test (logic-BIST) circuit, comprising:
causing the logic-BIST circuit to perform the following:
(a) initializing a set of flip-flops and memories of the logic block, the set of flip-flops connected to a clock signal and a reset signal, by writing to the flip-flops and memories known values of the reset signal during a same number of clock cycles;
(b) triggering the pattern generator to generate a set of test signals for processing by the logic block; and
(c) causing the signature accumulator to produce a test signature based on a set of outputs produced by the logic block upon processing the test signals; and
comparing the test signature to a reference signature, the reference signature representing the result of fault-free processing of the set of test signals by the logic block;
wherein initializing the set of flip-flops and memories causes them to simultaneously store the known values despite timing variations or propagation delays of the reset signal across the set of flip-flops.
22. A method as recited in claim 21 , the logic-BIST circuit for initializing the set of flip-flops and memories by performing the following sequence:
(f) gating the clock signal;
(g) activating the reset signal;
(h) resuming the clock signal while holding the reset signal active;
(i) gating the clock signal again; and
(j) deactivating the reset signal.
23. A method as recited in claim 22 , wherein the reference signature is computed by simulating fault-free operation of the logic block on the set of test signals.
24. A method as recited in claim 22 , wherein the logic block comprises a video decoder logic block for decoding video signals, and the pattern generator generates the set of test signals according to a standard selected from the group consisting of NTSC, PAL, SECAM, composite video, S-video, and component video.
25. A method as recited in claim 22 , wherein the signature accumulator comprises a linear feedback shift register (LFSR) for producing the test signature by incrementally compressing the set of outputs produced by the logic block.
26. A method as recited in claim 22 , wherein the logic-BIST circuit determines the times at which the signature accumulator reads the set of outputs produced by the logic block.
27. Computer program product for testing a logic block having a set of flip-flops connected to a clock signal and a reset signal, comprising:
computer code for initializing the set of flip-flops by writing to the flip-flops known values of the reset signal during a same number of clock cycles;
computer code for generating a set of test signals for processing by the logic block; and
computer code for producing a test signature based on a set of outputs produced by the logic block upon processing the test signals; and
computer readable medium for storing the computer code;
wherein initializing the set of flip-flops causes them to simultaneously store the known values despite timing variations or propagation delays of the reset signal across the set of flip-flops.
28. Computer program product as recited in claim 27 , wherein the computer code for initializing the set of flip flops comprises:
computer code for simultaneously storing known values despite timing variations or propagation delays of the reset signal across the set of flip-flops.
29. Computer program product as recited in claim 28 , wherein computer code for initializing the set of flip-flops comprises:
computer code for gating the clock signal;
computer code for activating the reset signal;
computer code for resuming the clock signal while holding the reset signal active;
computer code for gating the clock signal again; and
computer code for deactivating the reset signal.
30. Computer program product as recited in claim 29 , further comprising:
computer code for comparing the test signature to a reference signature, the reference signature representing the result of fault-free processing of the set of test signals by the logic block.
31. Computer program product as recited in claim 30 , wherein the reference signature is computed by simulating fault-free operation of the logic block on the set of test signals.
32. Computer program product as recited in claim 31 , wherein the logic block comprises a video decoder logic block for decoding video signals, and the set of test signals are generated according to a standard selected from the group consisting of NTSC, PAL, SECAM, composite video, S-video, and component video.