Reconfigurable interconnect for use in software-defined radio systems
View Patent ↗A method of fabricating an interconnect circuit for coupling a plurality of reconfigurable component blocks that implement a defined function. The method comprises the steps of: 1) determining P possible configurations for implementing the defined function; 2) for each of the P possible configuration, determining a list of required interconnections between the plurality of reconfigurable component blocks; 3) determining from the P lists of required interconnections a minimum number, B, of data buses required to implement the P possible configurations for the defined function; 4) for each of the P possible configurations, determining the interconnections of each of the plurality of reconfigurable component blocks to each of the B buses; and 5) implementing programmable switches capable of coupling a first reconfigurable component block to a first bus only if required to implement at least one of the P possible configurations.
1. A method of fabricating an interconnect circuit for coupling a plurality of context-based reconfigurable instruction set processors (CRISPs) that are reconfigurable within a context to implement at least one defined function, the context defining a group of operations related to a function, the method comprising the steps of:
determining, by at least one of the plurality of CRISPS, P possible configurations for implementing the at least one defined function;
for each of the P possible configurations, determining a list of required interconnections between the plurality of CRISPS;
determining from the P lists of required interconnections a minimum number, B, of data buses required to implement the P possible configurations for the at least one defined function;
for each of the P possible configurations, determining the interconnections of each of the plurality of CRISPs to each of the B buses; and
implementing programmable switches capable of coupling a first CRISP to a first bus only if required to implement at least one of the P possible configurations, wherein two or more of the CRISPS in the interconnect circuit are used to implement the at least one of the P possible configurations, wherein at least one other function is implemented in the interconnect circuit, and wherein power may be selectively applied to either one or both of the at least one defined function and the at least one other function.
2. The method as set forth in claim 1 , wherein the defined function is a correlation function.
3. The method as set forth in claim 1 , wherein the defined function is a signal decoding function.
4. The method as set forth in claim 1 , wherein the defined function is a Viterbi signal decoding function.
5. The method as set forth in claim 1 , wherein the defined function is a signal transform function.
6. The method as set forth in claim 1 , wherein the defined function is a Fast Fourier transform function.
7. The method as set forth in claim 1 , wherein the defined function is a baseband signal processing function.
8. A reconfigurable integrated circuit configurable in P possible configurations associated with a defined function, said reconfigurable integrated circuit comprising:
a plurality of context-based reconfigurable instruction set processors (CRISPS), each of said plurality of CRISPS reconfigurable based on a context, the context comprising a group of operations related to a function;
B data buses;
N input interfaces associated with said plurality of CRISPs, each of said N input interfaces selectively coupled to said B data buses; and
a first plurality of programmable switches, wherein each of said first plurality of programmable switches couples one of said N input interfaces to one of said B data buses only if required to implement a first P configuration associated with a first function and a second P configuration associated with a second function, and wherein power is selectively applied to either one or both of the first function and the second function.
9. The reconfigurable integrated circuit as set forth in claim 8 , further comprising:
M output interfaces associated with said plurality of CRISPs, each of said M output interfaces selectively coupled to said B data buses; and
a second plurality of programmable switches, wherein each of said second plurality of programmable switches couples one of said M output interfaces to one of said B data buses only if required to implement at least one of said P possible configurations.
10. The reconfigurable integrated circuit as set forth in claim 8 , wherein the defined function is a correlation function.
11. The reconfigurable integrated circuit as set forth in claim 8 , wherein the defined function is a signal decoding function.
12. The reconfigurable integrated circuit as set forth in claim 8 , wherein the defined function is a Viterbi signal decoding function.
13. The reconfigurable integrated circuit as set forth in claim 8 , wherein the defined function is a signal transform function.
14. The reconfigurable integrated circuit as set forth in claim 8 , wherein the defined function is a Fast Fourier transform function.
15. The reconfigurable integrated circuit as set forth in claim 8 , wherein the defined function is a baseband signal processing function.
16. The reconfigurable integrated circuit as set forth in claim 8 , wherein the reconfigurable integrated circuit is implemented in a software-defined radio system.
17. The reconfigurable integrated circuit as set forth in claim 16 , wherein the reconfigurable integrated circuit comprises a baseband signal processing subsystem in said software-defined radio system.
18. The reconfigurable integrated circuit as set forth in claim 16 , wherein the reconfigurable integrated circuit comprises an application layer processing subsystem in said software-defined radio system.
19. The reconfigurable integrated circuit as set forth in claim 8 , wherein at least one of the plurality of CRISPS is configured to implement a subset of the group of operations.
20. A reconfigurable integrated circuit configurable in P possible configurations associated with a defined function, said reconfigurable integrated circuit comprising:
a plurality of context-based reconfigurable instruction set processors (CRISPS), each of said plurality of CRISPS reconfigurable based on a context, the context comprising a group of operations related to a function, wherein a first of the plurality of CRISPS is configured to perform a first subset of the group of operations related to the function and a second of the plurality of CRISPS is configured to perform a second subset of the group of operations related to the function;
B data buses;
N input interfaces associated with said plurality of CRISPs, each of said N input interfaces selectively coupled to said B data buses; and
a first plurality of programmable switches, wherein each of said first plurality of programmable switches couples one of said N input interfaces to one of said B data buses only if required to implement a first P configuration associated with a first function and a second P configuration associated with a second function, and wherein power is selectively applied to either one or both of the first function and the second function.