Semiconductor storage device

1. A semiconductor storage device in which a plurality of pairs of wiring lines extending in a first direction are arranged repeatedly with a predetermined pitch, comprising:

a group of pair transistors in which a plurality of pair transistors having a same amplifying function is arranged according to a predetermined structural pattern, each of said pair transistors is connected to a respective pair of said plurality of pairs of wiring lines and is composed of a MOS transistor of which a gate is connected to one line of said respective pair of wiring lines and of another MOS transistor of which a gate is connected to the other line of said respective pair of wiring lines,

wherein said predetermined structural pattern forms a repetition unit that is repeated for the plurality of pairs of wiring lines, one of said pair transistors of the repetition unit having two MOS transistors that are adjacent to each other in said first direction, and at least one of said pair transistors of the repetition unit having two MOS transistors that are not adjacent to each other and are diagonally opposite to each other.

2. A semiconductor storage device according to claim 1 , wherein said repetition unit is formed of a rectangle area including six MOS transistors that are arranged in three stages in said first direction while being arranged in two stages in a direction perpendicular to said first direction, and comprises

first pair transistors composed of a MOS transistor positioned in a predetermined corner of said rectangle area and another MOS transistor adjacent to said MOS transistor in said first direction,

second pair transistors composed of a MOS transistor positioned in a corner diagonally opposite to said predetermined corner of said rectangle area and another MOS transistor adjacent to said MOS transistor in said first direction, and

third pair transistors composed of two MOS transistors which are not included in said first pair transistors nor said second pair transistors, not adjacent to each other, and arranged in a diagonal direction.

3. A semiconductor storage device according to claim 1 , wherein said repetition unit is formed of a rectangle area including eight MOS transistors that are arranged in three stages in said first direction while being arranged in three stages in a direction perpendicular to said first direction except a central region, and comprises

first pair transistors composed of a MOS transistor positioned in a predetermined corner of said rectangle area and another MOS transistor adjacent to said MOS transistor in said first direction,

second pair transistors composed of a MOS transistor positioned in a corner diagonally opposite to said predetermined corner of said rectangle area and another MOS transistor adjacent to said MOS transistor in said first direction,

third pair transistors composed of two MOS transistors which are not included in said first pair transistors nor said second pair transistors, not adjacent to each other, and arranged in a diagonal direction, and

fourth pair transistors composed of two MOS transistors which are not included in said first pair transistors, said second pair transistors nor said third pair transistors, not adjacent to each other, and arranged in a diagonally direction.

4. A semiconductor storage device according to claim 3 , wherein a non-active MOS transistor is arranged in said central region.

5. A semiconductor storage device according to any one of claims 1 to 4 , wherein said pairs of wiring lines are pairs of bit lines and said group of pair transistors is for use in a sense amplifier circuit that detects potentials of pairs of bit lines connected to a memory cell array and that amplifies minute potential differences therebetween, and

said pairs of bit lines extend in a bit line direction that is said first direction.

6. A semiconductor storage device according to claim 1 , wherein said gate of said MOS transistor is formed in the shape of a ring.

7. A semiconductor storage device according to claim 1 , wherein said gate of said MOS transistor is formed in the shape of a U.