System and method for information handling system clock source insitu diagnostics
View Patent ↗A clock diagnostics module, such as a state machine, integrated into an integrated clock controller monitors clock signals associated with the integrated clock controller and reports the status of the clock signals through a management bus, such as an SMBus. For instance, a counter integrated into the integrated clock controller counts clock signal cycles that occur in a management bus cycle and compares the clock signal with an expected value to determine the accuracy of the clock. A power on reset allows the management bus to read the clock diagnostics module in the event of clock controller failure.
1. A system for providing a clock signal to an information handling system, the system comprising:
an oscillator operable to provide a signal having a predetermined frequency;
a clock controller interfaced with the oscillator and operable apply the oscillator signal to generate one or more clock signals;
a management bus interface integrated with the clock controller and operable to communicate management information with a management bus; and
a clock diagnostics state machine integrated with the clock controller and interfaced with the management bus interface, the clock diagnostics state machine operable to compare the clock signal with a predetermined clock signal and communicate results of the comparison through the management bus interface to the management bus.
2. The system of claim 1 wherein the management bus is a SMBus.
3. The system of claim 1 wherein the predetermined clock signal comprises the oscillator frequency.
4. The system of claim 1 wherein the predetermined clock signal comprises a phased lock loop signal.
5. The system of claim 1 wherein the predetermined clock signal comprises a clock controller clock signal.
6. The system of claim 1 wherein the clock diagnostics state machine further comprises a counter operable to count up with the clock signal for a predetermined diagnostics time associated with a frequency of the management bus.
7. The system of claim 1 wherein the clock diagnostics state machine further comprises a counter operable to count down with the clock signal for a predetermined diagnostics time associated with a frequency of the management bus.
8. The system of claim 1 further comprising:
a clock diagnostics engine operating on a management system and operable to communicate with the clock diagnostics state machine through a management bus to read the results of the comparison by a power on reset.
9. A method for diagnosis of an information handling system clock signal, the method comprising:
generating a clock signal with an integrated clock controller;
communicating the clock signal to processing components of the information handling system through a clock bus;
communicating management information between the information handling system processing components through a management bus;
monitoring the clock signal with diagnostics circuitry embedded on the integrated clock controller; and
communicating monitoring information from the diagnostics circuitry through the management bus.
10. The method of claim 9 wherein the management bus comprises a SMBus.
11. The method of claim 9 wherein clock signal comprises the frequency of an oscillator associated with the integrated clock controller.
12. The method of claim 9 wherein the clock signal comprises a phase lock loop clock signal.
13. The method of claim 9 wherein the clock signal comprises an integrated clock controller clock signal output.
14. The method of claim 9 wherein monitoring further comprises:
counting the clock signal with the diagnostics circuitry for a management bus cycle time; and
diagnosing a clock controller failure if the clock signal count is not a predetermined count associated with the management bus cycle time.
15. The method of claim 9 wherein communicating further comprises:
applying a power on reset to the integrated clock controller to read clock diagnostics circuitry information.
16. An information handling system comprising:
a CPU operable to process information;
memory operable to store the information;
a primary bus operable to communicate the information between the CPU and memory at a clock signal;
a clock controller interfaced with the primary bus and operable to generate the clock signal;
a management processor operable to process management information;
a management bus interfaced with the management processor and operable to communicate the management information; and
a clock diagnostics module integrated with the clock controller and interfaced with the management bus, the clock diagnostics module operable to compare the clock signal with a management bus signal and communicate results of the comparison through the management bus to the management processor.
17. The information handling system of claim 16 further comprising:
a processing component interfaced with the primary bus to receive the clock signal and interfaced with the management bus;
a clock diagnostics module integrated with the processing component and interfaced with the management bus, the clock diagnostics module operable to compare the clock signal at the processing component with a management bus signal and communicated results of the comparison through The management bus to the management processor.
18. The information handling system of claim 16 wherein the management bus comprises a serial bus.
19. The information handling system of claim 16 further comprising a power on reset associated with the clock diagnostics module, the power on reset operable to communicate clock diagnostics information from the clock diagnostics module in the event of a primary bus clock signal failure.
20. The information handling system of claim 16 wherein the clock diagnostics module comprises a counter operable to compare the number of clock signals on the primary bus with predetermined signals sent by the management bus.