IP Library Patent Application 11146450
Patent Application
App. No. 11/146,450

Addressing scheme supporting variable local addressing and variable global addressing

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Quick Facts
Patent No.
US None
App. No.
11/146,450
Abstract

A node comprises at least one agent and an input/output (I/O) circuit coupled to an interconnect within the node. The I/O circuit is configured to communicate on a global interconnect to which one or more other nodes are coupled during use. Addresses transmitted on the interconnect are in a first local address space of the node, and addresses transmitted on the global interconnect are in a global address space. The first local address space includes at least a first region used to address at least a first resource of the node. The node is programmable, during use, to relocate the first region within the first local address space, whereby a same numerical value in the first local address space and a second local address space corresponding to one of the other nodes coupled to the global interconnect refers to the first resource in the node during use.

Claims (6)

1 - 19 . (canceled)

20 . A method comprising:

configuring a first node to map a first region of a global address space to a second region of a first local address space within the first node, the second region defined to address at least one resource in the first node; and

programming the first node to relocate the second region within the first local address space, whereby a same numerical value is used in the first local address space and in the global address space to address a location in the first region.

21 . The method as recited in claim 20 wherein configuring the first node comprises programming a global address to local address map storage in the first node to map the second region to the first region.

22 . The method as recited in claim 20 further comprising programming a second node to map one or more regions in a second local address space of the second node such that a third region having a same numerical value as the second region and the first region is mapped to the global address space.

Assignments (3)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →