Nonvolatile memory device

1. A nonvolatile memory device, comprising:

a first semiconductor layer of a first conductivity type in which a first region, a second region, and a third region are partitioned by an isolation insulating layer;

a first semiconductor section of a second conductivity type provided in the first region and functioning as a control gate;

a second semiconductor section of the first conductivity type provided in the second region;

a third semiconductor section of the second conductivity type provided in the third region;

an insulating layer provided on the semiconductor layer in the first to third regions;

a floating gate electrode provided on the insulating layer across the first to third regions;

first impurity regions of the first conductivity type provided on each side of the floating gate electrode in the first region;

second impurity regions of the second conductivity type provided on each side of the floating gate electrode in the second region and functioning as either a source region or a drain region; and

third impurity regions of the first conductivity type provided on each side of the floating gate electrode in the third region and functioning as either a source region or a drain region,

wherein an overlapping area of the floating sate electrode and the first semiconductor section is greater than an overlapping area of the floating gate electrode and the second semiconductor section.

2. The nonvolatile memory device as defined in claim 1 ,

wherein the first semiconductor section and the third semiconductor section are N-type wells.

3. A nonvolatile memory device, comprising:

a semiconductor layer of a first conductivity type in which a first region, a second region, and a third region are partitioned by an isolation insulating layer;

a first semiconductor section of a second conductivity type provided in the first region and functioning as a control gate;

a second semiconductor section of the first conductivity type provided in the second region;

a third semiconductor section of the second conductivity type provided in the third region;

an insulating layer provided on the semiconductor layer in the first to third regions;

a floating gate electrode provided on the insulating layer across the first to third regions;

first impurity regions of the first conductivity type provided on each side of the floating gate electrode in the first region;

second impurity regions of the second conductivity type provided on each side of the floating gate electrode in the second region and functioning as either a source region or a drain region; and

third impurity regions of the first conductivity type provided on each side of the floating gate electrode in the third region and functioning as either a source region or a drain region,

wherein a ratio of a total overlapping area of the floating gate electrode and the semiconductor layer in the first to third regions to an overlapping area of the first semiconductor section and the floating gate electrode in the first region is 10:6 to 10:9.

4. A nonvolatile memory device, comprising:

a semiconductor layer of a first conductivity type in which a first region, a second region and a third region are partitioned by an isolation insulating layer;

an insulating layer provided on the semiconductor layer;

a floating gate electrode provided on the insulating layer;

the insulating layer and the floating gate electrode provided across the first to third regions,

wherein in the first region, a first semiconductor section of a second conductivity type and first impurity regions of the first conductivity type are provided, the first semiconductor section of the second conductivity type provided in the semiconductor layer and functioning as a control gate, and the first impurity regions of the first conductivity type provided on each side of the floating gate electrode,

in the second region, a second semiconductor section of the first conductivity type and second impurity regions of the second conductivity type are provided, the second semiconductor section of the first conductivity type provided in the semiconductor layer, and the second impurity regions of the second conductivity type functioning as either a source region or a drain region and provided on each side of the floating gate electrode,

in the third region, a third semiconductor section of the second conductivity type and third impurity regions of the first conductivity type are provided, the third semiconductor section of the second conductivity type provided in the semiconductor layer, and the third impurity regions of the first conductivity type provided on each side of the floating gate electrode and functioning as either a source region or a drain region, and

wherein an overlapping area of the floating gate electrode and the first semiconductor section is greater than an overlapping area of the floating gate electrode and the semiconductor layer in the second region.

5. The nonvolatile memory device as defined in claim 4 ,

wherein the first and third semiconductor sections are N-type wells.

6. The nonvolatile memory device as defined in claim 4 ,

wherein the semiconductor layer is a semiconductor substrate, and the first, second and third semiconductor sections are parts of the semiconductor substrate in which impurities are implanted.

7. A nonvolatile memory device, comprising:

a semiconductor layer of a first conductivity type in which a first region, a second region and a third region are partitioned by an isolation insulating layer;

an insulating layer provided on the semiconductor layer;

a floating gate electrode provided on the insulating layer;

the insulating layer and the floating gate electrode provided across the first to third regions,

wherein in the first region, a first semiconductor section of a second conductivity type and first impurity regions of the first conductivity type are provided, the first semiconductor section of the second conductivity type provided in the semiconductor layer and functioning as a control gate, and the first impurity regions of the first conductivity type provided on each side of the floating gate electrode,

in the second region, a second semiconductor section of the first conductivity type and second impurity regions of the second conductivity type are provided, the second semiconductor section of the first conductivity type provided in the semiconductor layer, and the second impurity regions of the second conductivity type provided on each side of the floating gate electrode and functioning as either a source region or a drain region,

in the third region, a third semiconductor section of the second conductivity type and third impurity regions of the first conductivity type are provided, the third semiconductor section of the second conductivity type provided in the semiconductor layer, and the third impurity regions of the first conductivity type provided on each side of the floating gate electrode and functioning as either a source region or a drain region, and

wherein a ratio of a total overlapping area of the floating gate electrode and the semiconductor layer in the first, second and third regions to an overlapping area of the first semiconductor section and the floating gate electrode is 10:6 to 10:9.

8. The nonvolatile memory device as defined in claim 7 , wherein the semiconductor layer is a semiconductor substrate, and the first, second and third semiconductor sections are parts of the semiconductor substrate in which impurities are implanted.