Semiconductor device and method for fabricating the same
View Patent ↗A semiconductor device in which a semiconductor layer of a thin film transistor and a first electrode of a capacitor are formed of amorphous silicon and the whole or a part of source/drain regions of the semiconductor layer and the first electrode of the capacitor are crystallized by a metal induced crystallization method, and a channel region of the semiconductor layer is crystallized by a metal induced lateral crystallization method.
1. A semiconductor device, comprising:
a substrate;
a thin film transistor on the substrate and comprising a semiconductor layer having source/drain regions with regions that have a first crystalline structure formed by a metal induced crystallization method and a channel region that has a second crystalline structure formed by a metal induced lateral crystallization method; and
a capacitor spaced apart from the thin film transistor and comprising a first electrode having the first crystalline structure formed by the metal induced crystallization method,
wherein the first crystalline structure is a different crystalline structure than the second crystalline structure.
2. The semiconductor device of claim 1 , wherein the source/drain regions further have regions that have the second crystalline structure formed by the metal induced lateral crystallization method.
3. The semiconductor device of claim 1 , wherein a crystallization inducing material used in the metal induced crystallization method or the metal induced lateral crystallization method is a metal silicide in which any one or more metals selected from Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Mo, Tr, Ru, Rh, Cd and Pt are silicided.
4. The semiconductor device of claim 1 , wherein a crystallization inducing material used in the metal induced crystallization method or the metal induced lateral crystallization method is nickel silicide.
5. The semiconductor device of claim 1 , wherein the source/drain regions and the channel region are crystallized by performing heat treatment at 400° C. to 700° C. for 1 to 18 hours.
6. The semiconductor device of claim 1 , wherein the source/drain regions and the channel region are crystallized by performing heat treatment at 500° C. to 600° C. for 3 to 12 hours.
7. The semiconductor device of claim 1 , wherein the thin film transistor further comprises a gate insulation layer on the semiconductor layer, the gate insulation layer includes at least two insulating layers.
8. The semiconductor device of claim 7 , wherein the at least two layers of the gate insulation layer are both arranged between the gate electrode and the semiconductor layer.
9. The semiconductor device of claim 8 , wherein a first layer of the at least two layers contacts the channel region only of the semiconductor layer.
10. The semiconductor device of claim 9 , wherein a second layer of the at least two layers extends to be arranged between electrodes of the capacitor.
11. The semiconductor device of claim 8 , wherein a first layer of the at least two layers contacts the source/drain regions and the channel region of the semiconductor layer.
12. The semiconductor device of claim 11 , wherein the first layer of the at least two layers extends to be arranged between electrodes of the capacitor.
13. The semiconductor device of claim 1 , wherein the thin film transistor further comprises a gate insulator on the semiconductor layer and the capacitor further comprises an insulation layer, the insulation layer of the capacitor being formed of the same layer as a second layer of the gate insulator.
14. The semiconductor device of claim 1 , wherein the thin film transistor further comprises a gate electrode and the capacitor further comprises a second electrode, and wherein the gate electrode and the second electrode are formed of the same material.