Method of growing a germanium epitaxial film on insulator for use in fabrication of CMOS integrated circuit

1. A method of fabricating a silicon-germanium CMOS comprising:

preparing a silicon substrate wafer;

depositing an insulating layer on the silicon substrate wafer;

patterning and etching the insulating layer;

depositing a layer of polycrystalline germanium on the insulating layer and on at least a portion of the silicon substrate wafer to form a silicon/germanium interface;

patterning and etching the polycrystalline germanium;

encapsulating the polycrystalline germanium with an insulating layer;

rapidly thermally annealing the wafer at a temperature sufficient to melt the polycrystalline germanium;

cooling the wafer to promote liquid phase epitaxy of the polycrystalline germanium beginning at the silicon/germanium interface and extending laterally therefrom, thereby forming a single crystal germanium layer; and

completing the CMOS device.

2. The method of claim 1 wherein said preparing a silicon substrate wafer includes forming a silicon-based CMOS on the silicon substrate wafer.

3. The method of claim 1 wherein said depositing a layer of polycrystalline germanium includes depositing a layer of polycrystalline germanium to a thickness of between about 5 nm to 100 nm.

4. The method of claim 1 wherein said rapidly thermally annealing the wafer includes heating the wafer to a temperature of between about 920° C. to 1000° C.

5. The method of claim 1 wherein said completing the CMOS includes source/drain and gate salicidation of a germanium-based CMOS device.

6. A method of fabricating a silicon-germanium CMOS comprising:

preparing a silicon substrate wafer, including forming a silicon-based CMOS thereon;

forming a germanium-based CMOS on the silicon-based CMOS, including depositing an insulating layer on the silicon substrate wafer;

patterning and etching the insulating layer;

depositing a layer of polycrystalline germanium on the insulating layer and on at least a portion of the silicon substrate wafer to form a silicon/germanium interface;

patterning and etching the polycrystalline germanium;

encapsulating the polycrystalline germanium with an insulating layer;

rapidly thermally annealing the wafer at a temperature sufficient to melt the polycrystalline germanium;

cooling the wafer to promote liquid phase epitaxy of the polycrystalline germanium beginning at the silicon/germanium interface and extending laterally therefrom, thereby forming a single crystal germanium layer; and

completing the germanium-based CMOS device.

7. The method of claim 6 wherein said depositing a layer of polycrystalline germanium includes depositing a layer of polycrystalline germanium to a thickness of between about 5 nm to 100 nm.

8. The method of claim 6 wherein said rapidly thermally annealing the wafer includes heating the wafer to a temperature of between about 920° C. to 1000° C.

9. The method of claim 6 wherein said completing the CMOS includes source/drain and gate salicidation of the germanium-based CMOS device.

10. A method of fabricating a silicon-germanium CMOS comprising:

preparing a silicon substrate wafer;

depositing an insulating layer on the silicon substrate wafer;

patterning and etching the insulating layer;

depositing a layer of polycrystalline germanium, to a thickness of between about 5 nm to 100 nm, on the insulating layer and on at least a portion of the silicon substrate wafer to form a silicon/germanium interface;

patterning and etching the polycrystalline germanium;

encapsulating the polycrystalline germanium with an insulating layer;

rapidly thermally annealing the wafer at a temperature a temperature of between about 920° C. to 1000° C. to melt the polycrystalline germanium while not melting the silicon substrate wafer and the insulating layer;

cooling the wafer to promote liquid phase epitaxy of the polycrystalline germanium beginning at the silicon/germanium interface and extending laterally therefrom, thereby forming a single crystal germanium layer; and

completing the CMOS device.

11. The method of claim 10 wherein said preparing a silicon substrate wafer includes forming a silicon-based CMOS on the silicon substrate wafer.

12. The method of claim 10 wherein said completing the CMOS includes source/drain and gate salicidation of a germanium-based CMOS device.