Organic thin-film transistor, method of fabricating the same, and flat panel display having the same
View Patent ↗The present invention relates to an organic thin film transistor (OTFT), a method of fabricating the OTFT, and an organic electroluminescent display that has the OTFTs. The invention prevents surface damage of an organic semiconductor layer and reduces an off-current. The OTFT includes a substrate, a source electrode and a drain electrode formed on the substrate, and a semiconductor layer formed on the substrate that has a channel layer disposed over and between the source electrode and drain electrode. In addition, the OTFT includes a gate insulating layer formed on the semiconductor layer, a separation pattern formed through the semiconductor layer and the gate insulating layer to separate the channel layer, and a gate electrode formed on the gate insulating layer over the channel layer.
1. A method of fabricating a TFT, comprising:
forming a source electrode and a drain electrode on a substrate;
forming a semiconductor layer disposed on the source electrode and the drain electrode and the substrate and having a channel layer;
forming a gate insulating layer on the semiconductor layer;
patterning the gate insulating layer and the semiconductor layer, thereby forming a separation pattern; and
forming a gate electrode on the gate insulating layer over the channel layer,
wherein the separation pattern is surrounded by the gate insulating layer and the semiconductor layer.
2. The method of claim 1 , wherein the substrate includes a plastic substrate.
3. The method of claim 1 , wherein the semiconductor layer includes an organic semiconductor layer.
4. The method of claim 1 , wherein the separation pattern has a groove shape.
5. The method of claim 4 , wherein the separation pattern has a closed loop shape.
6. The method of claim 4 , wherein the separation pattern has a shape of at least one pair of parallel lines.
7. The method of claim 1 , wherein the gate insulating layer includes a first gate insulating layer and a second gate insulating layer; and
wherein the separation pattern is formed through the semiconductor layer and the first gate insulating layer.
8. The method of claim 1 , wherein the separation pattern is formed using a laser ablation method.
9. The method of claim 1 , wherein the source electrode and the drain electrode are disposed in a pixel area, and the gate insulating layer and the semiconductor layer are arranged on both sides of the separation pattern in the pixel area.
10. A method of fabricating a TFT, comprising:
forming a source electrode and a drain electrode on a substrate;
forming an organic semiconductor layer disposed on the source electrode and the drain electrode and the substrate and having a channel layer;
forming a first gate insulating layer on the organic semiconductor layer;
patterning the first gate insulating layer and the organic semiconductor layer after forming the first gate insulating layer on the organic semiconductor layer, thereby forming a separation pattern; and
forming a gate electrode on the first gate insulating layer over the channel layer,
wherein the separation pattern is surrounded by the gate insulating layer and the semiconductor layer.
11. The method of claim 10 , wherein the substrate includes a plastic substrate.
12. The method of claim 10 , wherein the first gate insulating layer is an organic layer.
13. The method of claim 10 , wherein the separation pattern has a groove shape.
14. The method of claim 13 , wherein the separation pattern has a closed loop shape.
15. The method of claim 13 , wherein the separation pattern has a shape of at least one pair of parallel lines.
16. The method of claim 10 , wherein the separation pattern is formed using a laser ablation method.
17. The method of claim 10 , further comprising:
forming a second gate insulating layer on the first gate insulating layer after patterning the first gate insulating layer and the organic semiconductor layer,
wherein the gate electrode is formed directly on the second gate insulating layer.
18. The method of claim 17 , wherein the second gate insulating layer contacts the organic semiconductor layer via the separation pattern.
19. The method of claim 17 , wherein the first gate insulating layer and the second gate insulating layer are both organic layers.
20. The method of claim 10 , wherein the source electrode and the drain electrode are disposed in a pixel area, and the gate insulating layer and the semiconductor layer are arranged on both sides of the separation pattern in the pixel area.