Method and system for a gigabit ethernet IP telephone chip
View Patent ↗Methods and systems for processing Ethernet data are disclosed and may comprise receiving packetized data by an Ethernet switch integrated within a single gigabit Ethernet IP phone chip. A first portion of the received packetized data may be switched within the single gigabit Ethernet IP phone chip, between a first on-chip port that routes data internally for processing within the single gigabit Ethernet IP phone chip and a second on-chip port that routes data externally for off-chip processing. The packetized data may be received by a 10/100Base Ethernet physical interface transceiver (PHY) integrated within the single gigabit Ethernet IP phone chip. The packetized data may be received by a gigabit Ethernet PHY. The received packetized data may be communicated from the gigabit Ethernet PHY to the Ethernet switch integrated within the single gigabit Ethernet IP phone chip for switching.
1. A method for communication, the method comprising:
performing in a single gigabit Ethernet IP phone chip:
receiving packetized data by an Ethernet switch integrated within said single gigabit Ethernet IP phone chip, wherein said Ethernet switch comprises a first on-chip port that routes data internally for on-chip processing and a second on-chip port that routes data externally for off-chip processing:
communicating, via said first on-chip port of said Ethernet switch, portions of said received packetized data comprising video content to one or more peripheral interfaces integrated within said single gigabit Ethernet IP phone chip; and
communicating, via said one or more peripheral interfaces, said video content to a video processing device communicatively coupled to said gigabit Ethernet IP phone chip;
routing said received packetized data comprising said video content via said second on-chip port; and
routing said received packetized data comprising said video content to a gigabit Ethernet PHY.
2. The method according to claim 1 , comprising receiving said packetized data by a 10/100BASE Ethernet physical interface transceiver (PHY) integrated within said single gigabit Ethernet IP phone chip.
3. The method according to claim 1 , comprising receiving said packetized data via a gigabit Ethernet physical interface transceiver (PHY), wherein said gigabit Ethernet PHY is external to said single gigabit Ethernet IP phone chip.
4. The method according to claim 3 , wherein said received packetized data is communicated from said gigabit Ethernet PHY to said Ethernet switch integrated within said single gigabit Ethernet IP phone chip for switching.
5. The method according to claim 1 , wherein a remaining portion of said received packetized data comprises at least one of: packetized voice data and packetized network data.
6. The method according to claim 5 , comprising communicating one or both of said voice data and said network data internally, via said first on-chip port, for processing within said single gigabit Ethernet IP phone chip.
7. The method according to claim 5 , comprising communicating said voice data via said first on-chip port, and communicating said network data via said second on-chip port.
8. The method according to claim 5 , comprising communicating one or both of said voice data and said network data via said second on-chip port.
9. A system for processing Ethernet data, the system comprising:
a single gigabit Ethernet IP phone chip that comprises an Ethernet switch, wherein:
said Ethernet switch comprises a first on-chip port that routes data internally for on-chip processing and a second on-chip port that routes data externally for off-chip processing;
said Ethernet switch is operable to receive packetized data and communicate, via said first on-chip port, portions of said received packetized data comprising video, content to one or more peripheral interfaces integrated within said single gigabit Ethernet IP phone chip;
said Ethernet IP phone chip is operable to communicate, via one or more interfaces integrated within said single gigabit Ethernet IP phone chip, said video content to a video processing device communicatively coupled to said gigabit Ethernet IP phone chip;
said Ethernet switch is operable to route said received packetized data comprising said video content via said second on-chip port; and
said Ethernet switch is route said received packetized data comprising said video content to a gigabit Ethernet PHY.
10. The system according to claim 9 , comprising a 10/100Base Ethernet physical interface transceiver (PHY) integrated within said single gigabit Ethernet IP phone chip that receives said packetized data.
11. The system according to claim 9 , comprising a gigabit Ethernet PHY that is external to said single Ethernet IP phone chip that receives said packetized data.
12. The system according to claim 11 , wherein said gigabit Ethernet PHY communicates said received packetized data to said Ethernet switch integrated within said single gigabit Ethernet IP phone chip for switching.
13. The system according to claim 9 , wherein a remaining portion of said received packetized data comprises at least one of: packetized voice data and packetized network data.
14. The system according to claim 13 , wherein said Ethernet switch communicates one or both of said voice data and said network data internally, via said first on-chip port, for processing within said single gigabit Ethernet IP phone chip.
15. The system according to claim 13 , wherein said Ethernet switch communicates said voice data via said first on-chip port, and communicates said network data via said second on-chip port.
16. The system according to claim 13 , wherein said Ethernet switch communicates one or both of said voice data and said video data via said second on-chip port.
17. A system for communication, the system comprising:
one or more circuits for use in a single gigabit Ethernet IP phone chip, said one or more circuits comprising:
an Ethernet switch that comprises a first on-chip port that routes data internally for on-chip processing and a second on-chip port that routes data externally for off-chip processing; and
one or more peripheral interfaces;
wherein said one or more circuits are operable to:
receive packetized data;
communicate, via said first on-chip port of said Ethernet switch, portions of said received packetized data comprising video content to said one or more peripheral interfaces;
communicate, via said one or more peripheral interfaces, said video content to a video processing device communicatively coupled to said gigabit Ethernet IP phone chip;
route said received packetized data comprising said video content via said second on-chip port; and
route said received packetized data comprising said video content to a gigabit Ethernet PHY.
18. The system according to claim 17 , wherein said one or more circuits are operable to receive said packetized data via a 10/100Base Ethernet physical interface transceiver (PHY) integrated within said single gigabit Ethernet IP phone chip.
19. The system according to claim 17 , wherein said one or more circuits are operable to receive said packetized data via a gigabit Ethernet PHY that is external to said single gigabit Ethernet IP phone chip.
20. The system according to claim 19 , wherein said received packetized data is communicated from said gigabit Ethernet PHY to said Ethernet switch integrated within said single gigabit Ethernet IP phone chip for switching.
21. The system according to claim 17 , wherein a remaining portion of said received packetized data comprises at least one of: packetized voice data and packetized network data.
22. The system according to claim 21 , wherein said one or more circuits are operable to communicate one or both of said voice data and said network data internally, for processing within said single gigabit Ethernet IP phone chip.
23. The system according to claim 21 , wherein said one or more circuits are operable to communicate said voice data via said first on-chip port, and communicate said network data via said second on-chip port.
24. The system according to claim 21 , wherein said one or more circuits are operable to communicate one or both of said voice data and said network data via said second on-chip port.