Method and system for a gigabit Ethernet IP telephone chip with integrated DDR interface
View Patent ↗Methods and systems for processing data are disclosed herein and may comprise processing data via a single gigabit Ethernet IP telephone chip integrated within a gigabit Ethernet IP telephone. At least a portion of the processed data may be communicated to an off-chip DDR memory within the gigabit IP telephone via an on-chip DDR memory interface integrated within the gigabit IP telephone chip. The data may be acquired from the off-chip DDR memory via the DDR memory interface for the processing. A request to process the data may be received by the gigabit Ethernet IP telephone chip. The request for processing the data may comprise a Memory Read command, a Memory Write command, a Memory Write with Reply command, a Memory Swap command, an Input/Output (I/O) Read command, an I/O Write command, and/or an I/O Write with Reply command.
1. A method for processing data, the method comprising:
receiving a signal that requests access to a Double Data Rate Random Access Memory (DDR RAM) interface integrated within a single gigabit Ethernet IP telephone chip in a gigabit Ethernet IP telephone, wherein said signal is prioritized into one of a plurality of queues within said DDR RAM interface; and
looking ahead, by said DDR RAM interface based on said received prioritized signal, at least one pending transaction associated with said requested access, prior to communicating data associated with said at least one pending transaction between said gigabit Ethernet IP telephone chip and an off-chip DDR RAM communicatively coupled via said DDR RAM interface to said single gigabit Ethernet IP telephone chip.
2. The method according to claim 1 , comprising decoding said signal that requests access to said DDR RAM interface.
3. The method according to claim 2 , comprising determining an access type associated with said signal that requests access to said DDR RAM interface.
4. The method according to claim 3 , comprising determining based on said access type, whether said signal that requests access to said DDR RAM interface is one of the following: an access to said off-chip DDR RAM and an access to a pool of buffers in said off-chip DDR RAM.
5. The method according to claim 1 , wherein said received signal that requests access to said DDR RAM interface comprises one or more of a Memory Read memory access command, a Memory Write memory access command, a Memory Write with Reply memory access command, and/or a Memory Swap memory access command.
6. The method according to claim 1 , wherein said received signal that requests access to said DDR RAM interface comprises one or more of an Input/Output (I/O) Read buffer pool command, an I/O Write buffer pool command, and/or an I/O Write with Reply buffer pool command.
7. The method according to claim 1 , comprising arbitrating access to said off-chip DDR RAM via said DDR RAM interface.
8. The method according to claim 1 , comprising arbitrating access to said off-chip DDR RAM via said DDR RAM interface utilizing a weighted priority arbitration scheme.
9. The method according to claim 1 , comprising prioritizing access to said DDR RAM interface based on a source of said signal that requests access to said DDR RAM interface.
10. The method according to claim 1 , comprising queuing said signal that requests access to said DDR RAM interface in a high priority queue in said off-chip DDR RAM when said signal that requests access to said DDR RAM interface originates from a core processor within said single gigabit Ethernet IP telephone chip.
11. The method according to claim 10 , comprising queuing said signal that requests access to said DDR RAM interface in a low priority queue in said off-chip DDR RAM when said signal that requests access to said DDR RAM interface originates from a source other than said core processor.
12. A system for processing data, the system comprising:
at least one processor that enables receiving a signal that requests access to a DDR RAM interface integrated within a single gigabit Ethernet IP telephone chip in a gigabit Ethernet IP telephone, wherein said signal is prioritized into one of a plurality of queues within said DDR RAM interface; and
said at least one processor enables looking ahead, by said DDR RAM interface based on said received prioritized signal, at least one pending transaction associated with said requested access, prior to communication of data associated with said at least one pending transaction between said gigabit Ethernet IP telephone chip and an off-chip DDR RAM communicatively coupled via said DDR RAM interface to said single gigabit Ethernet IP telephone chip.
13. The system according to claim 12 , wherein said at least one processor enables decoding of said signal that requests access to said DDR RAM interface.
14. The system according to claim 13 , wherein said at least one processor enables determination of an access type associated with said signal that requests access to said DDR RAM interface.
15. The system according to claim 14 , wherein said at least one processor enables determination based on said access type, whether said signal that requests access to said DDR RAM interface is one of the following: an access to said off-chip DDR RAM and an access to a pool of buffers in said off-chip DDR RAM.
16. The system according to claim 12 , wherein said received signal that requests access to said DDR RAM interface comprises one or more of a Memory Read memory access command, a Memory Write memory access command, a Memory Write with Reply memory access command, and/or a Memory Swap memory access command.
17. The system according to claim 12 , wherein said received signal that requests access to said DDR RAM interface comprises one or more of an Input/Output (I/O) Read buffer pool command, an I/O Write buffer pool command, and/or an I/O Write with Reply buffer pool command.
18. The system according to claim 12 , wherein said at least one processor enables arbitration of access to said off-chip DDR RAM via said DDR RAM interface.
19. The system according to claim 12 wherein said at least one processor enables arbitration of access to said off-chip DDR RAM via said DDR RAM interface utilizing a weighted priority arbitration scheme.
20. The system according to claim 12 , wherein said at least one processor enables prioritization of access to said DDR RAM interface based on a source of said signal that requests access to said DDR RAM interface.
21. The system according to claim 12 , wherein said at least one processor enables queuing of said signal that requests access to said DDR RAM interface in a high priority queue in said off-chip DDR RAM, if said signal that requests access to said DDR RAM interface originates from a core processor within said single gigabit Ethernet IP telephone chip.
22. The system according to claim 21 , wherein said at least one processor enables queuing of said signal that requests access to said DDR RAM interface in a low priority queue in said off-chip DDR RAM, if said signal that requests access to said DDR RAM interface originates from a source other than said core processor.
23. The method according to claim 1 , wherein said looking ahead of said at least one pending transaction comprising determining whether to precharge an already opened memory bank, activate a new memory bank, or proceed to execute a memory access command.
24. The system according to claim 12 , wherein said looking ahead of said at least one pending transaction comprising determining whether to precharge an already opened memory bank, activate a new memory bank, or proceed to execute a memory access command.