Organic thin film transistor array panel and manufacturing method thereof
View Patent ↗A method of manufacturing a thin film transistor array panel is provided, the method including: forming a gate line on a substrate; forming a gate insulating layer on the gate line; forming a data line and a drain electrode on the gate insulating layer; forming an organic semiconductor layer on the data line, the drain electrode and an exposed portion of the gate insulating layer between the data line and the drain electrode; forming a protective member fully covering the organic semiconductor layer; forming a passivation layer on the protective layer, the data line, and the drain electrode; forming a contact hole in the passivation layer to expose a portion of the drain electrode; and forming a pixel electrode on the passivation layer, the pixel electrode connected to the drain electrode through the contact hole.
1. A method of manufacturing a thin film transistor array panel, the method comprising:
forming a gate line on a substrate;
forming a gate insulating layer on the gate line;
forming a data line and a drain electrode on the gate insulating layer;
forming an organic semiconductor layer on the data line, the drain electrode, and an exposed portion of the gate insulating layer between the data line and the drain electrode;
forming a protective member fully covering the organic semiconductor layer;
forming a passivation layer on the protective member, the data line, and the drain electrode;
forming a contact hole in the passivation layer to expose a portion of the drain electrode; and
forming a pixel electrode on the passivation layer, the pixel electrode being connected to the drain electrode through the contact hole, wherein the forming the protective member comprises:
depositing an insulating layer at a temperature equal to or lower than a room temperature; and
patterning the insulating layer in a dry manner to form the protective member.
2. The method of claim 1 , wherein the protective member comprises polyxylene polymer.
3. The method of claim 1 , wherein the organic semiconductor layer comprises at least one selected from the group consisting of:
tetracene, pentacene, and derivatives thereof with substituent;
oligothiophene including four to eight thiophenes connected at the positions 2, 5 of thiophene rings;
perylenetetracarboxylic dianhydride (PTCDA), naphthalenetetracarboxylic dianhydride (NTCDA), and imide derivatives thereof;
metallized phthalocyanine and halogenated derivatives thereof;
co-oligomer and co-polymer of thienylene and vinylene;
regioregular polythiophene;
perylene, coroene, and derivatives thereof with substituent; and
aromatic and heteroaromatic ring of the above-described materials with at least one hydrocarbon chain having one to thirty carbon atoms.
4. The method of claim 1 , wherein the gate insulating layer comprises at least one selected from the group consisting of silicon dioxide, silicon nitride, maleimide-styrene, polyvinylphenol (PVP), and modified cyanoethylpullulan (m-CEP).
5. The method of claim 4 , wherein the gate insulating layer has a surface treated with octadecyl-trichloro-silane.