Semiconductor device
View Patent ↗A semiconductor device includes a memory section formed at a semiconductor substrate and including a first transistor having an ONO film that can store charges between the semiconductor substrate and a memory electrode and a first STI region for isolating the first transistor, and a CMOS section formed at the semiconductor substrate and including a second transistor having a CMOS electrode and a gate dielectric and a second STI region for isolating the second transistor. The height of the top surface of the first STI region is set equal to or smaller than the height of the top surface of the second STI region.
1. A semiconductor device comprising:
a memory section formed in a semiconductor region and including a first gate structure having a first gate electrode and a first gate dielectric that is formed directly on the semiconductor region and can store charges between the semiconductor region and the first gate electrode and a first isolation region; and
a logic section formed in the semiconductor region and including a second gate structure having a second gate electrode and a second gate dielectric and a second isolation region,
wherein, in the memory section, the first gate dielectric and the first gate electrode are formed to partly cover the first isolation region,
in the logic section, the second gate electrode is formed to partly cover the second isolation region,
the height of the top surface of a part of the first isolation region partly covered with the first gate dielectric and the first gate electrode from the top surface of the semiconductor region is equal to or smaller than the height of the top surface of a part of the second isolation region partly covered with the second gate electrode therefrom,
a composition of the first gate dielectric is different from that of the second gate dielectric, and
the first gate dielectric is a multilayer film of silicon nitride and silicon oxide.
2. The device of claim 1 , wherein
the first gate dielectric is an ONO film (a multilayer film obtained by successively stacking a silicon oxide film, a silicon nitride film and a silicon oxide film).
3. The device of claim 1 , wherein
the first and second isolation regions are trench isolation regions.
4. The device of claim 1 , wherein
the memory section has a diffusion layer formed in the upper part of the semiconductor region, and
a metal silicide layer is formed on the diffusion layer.