Soft-error rate improvement in a latch using low-pass filtering
View Patent ↗In a preferred embodiment, the invention provides a circuit and method for reducing soft error events in latches. A low-pass filter is placed between the output of a forward inverter and the inputs of a feedback keeper. The first and second outputs of the low-pass filter are connected to first and second inputs respectively of the feedback keeper. The only type of diffusion connected to the first output of the low-pass filter is a P-type diffusion. The only type of diffusion connected to the second output of the low-pass filter is an N-type diffusion. The feedback keeper is connected to an input of the forward inverter.
1. A method of manufacturing a latch comprising:
a) connecting a low-pass filter between an output of a forward inverter and inputs of a feedback keeper;
b) connecting a first output of the low-pass filter to a first input of the feedback keeper;
c) connecting a second output of the low-pass filter to a second input of the feedback keeper;
d) such that the only type of diffusion attached to the first output of the low-pass filter is a P-type diffusion;
e) such that the only type of diffusion attached to the second output of the low-pass filter is an N-type diffusion;
f) wherein an output of the feedback keeper is connected to an input of the forward inverter.
2. The method as in claim 1 wherein the forward inverter comprises:
a) a PFET, the PFET having a gate, drain, and source;
b) an NFET, the NFET having a gate, drain, and source;
c) wherein the gates of the PFET and NFET are connected to the input of the forward inverter;
d) wherein the drains of the PFET and NFET are connected to the output of the forward inverter;
e) wherein the source of the PFET is connected to VDD;
f) wherein the source of the NFET is connected to GND.
3. The method as in claim 1 wherein the low-pass filter comprises:
a) a inverter, the inverter having an input and an output;
b) a first PFET, the first PFET having a gate, drain, and source;
c) a second PFET, the second PFET having a gate, drain, and source;
d) a third PFET, the third PFET having a gate, drain, and source;
e) a first NFET, the first NFET having a gate, drain, and source;
f) a second NFET, the second NFET having a gate, drain, and source;
g) a third NFET, the third NFET having a gate, drain, and source;
h) wherein the input of the low-pass filter is connected to the input of the inverter and the gates of the second PFET and the first NFET;
i) wherein the output of the inverter is connected to the gates of the first PFET and the second NFET;
j) wherein the sources of the first PFET, and the third PFET are connected to VDD;
k) wherein the drain of the first NFET is connected to VDD;
l) wherein the sources of the second NFET, and the third NFET are connected to GND;
m) wherein the drain of the second PFET is connected to GND;
n) wherein the gate of the third NFET is connected to a clock signal;
o) wherein the gate of the third PFET is connected to the opposite phase of the clock signal;
p) wherein the drains of the first PFET and third PFET and the source of the second PFET are connected to the first output of the low-pass filter;
q) wherein the drains of the second NFET and third NFET and the source of the first NFET are connected to the second output of the low-pass filter.
4. The method as in claim 3 wherein the inverter comprises:
a) a PFET, the PFET having a gate, drain, and source;
b) an NFET, the NFET having a gate, drain, and source;
c) wherein the gates of the PFET and NFET are connected to the input of the inverter;
d) wherein the drains of the PFET and NFET are connected to the output of the inverter;
e) wherein the source of the PFET is connected to VDD;
f) wherein the source of the NFET is connected to GND.
5. The method as in claim 1 wherein the feedback keeper comprises:
a) a PFET, the PFET having a gate, drain, and source;
b) an NFET, the NFET having a gate, drain, and source;
c) wherein the gate of the PFET is connected to the first input of the feedback keeper;
d) wherein the gate of the NFET is connected to the second input of the feedback keeper;
e) wherein the drains of the PFET and NFET are connected to the output of the feedback keeper;
f) wherein the source of the PFET is connected to VDD;
g) wherein the source of the NFET is connected to GND.
6. A latch comprising:
a) a forward inverter;
b) a feedback keeper;
c) a low-pass filter;
d) wherein an output of the forward inverter is connected to an input of the low-pass filter;
e) wherein a first output of the low-pass filter is connected to a first input of the feedback keeper;
f) such that the only type of diffusion attached to the first output of the low-pass filter is a P-type diffusion;
g) wherein a second output of the low-pass filter is connected to a second input of the feedback keeper;
h) such that the only type of diffusion attached to the second output of the low-pass filter is an N-type diffusion;
i) wherein an output of the feedback keeper is connected to the input of the forward inverter.
7. The latch as in claim 6 wherein the forward inverter comprises:
a) a PFET, the PFET having a gate, drain, and source;
b) an NFET, the NFET having a gate, drain, and source;
c) wherein the gates of the PFET and NFET are connected to the input of the forward inverter;
d) wherein the drains of the PFET and NFET are connected to the output of the forward inverter;
e) wherein the source of the PFET is connected to VDD;
f) wherein the source of the NFET is connected to GND.
8. The latch as in claim 6 wherein the low-pass filter comprises:
a) a inverter, the inverter having an input and an output;
b) a first PFET, the first PFET having a gate, drain, and source;
c) a second PFET, the second PFET having a gate, drain, and source;
d) a third PFET, the third PFET having a gate, drain, and source;
e) a first NFET, the first NFET having a gate, drain, and source;
f) a second NFET, the second NFET having a gate, drain, and source;
g) a third NFET, the third NFET having a gate, drain, and source;
h) wherein the input of the low-pass filter is connected to the input of the inverter and the gates of the second PFET and the first NFET;
i) wherein the output of the inverter is connected to the gates of the first PFET and the second NFET;
j) wherein the sources of the first PFET, and the third PFET are connected to VDD;
k) wherein the drain of the first NFET is connected to VDD;
l) wherein the sources of the second NFET, and the third NFET are connected to GND;
m) wherein the drain of the second PFET is connected to GND;
n) wherein the gate of the third NFET is connected to a clock signal;
o) wherein the gate of the third PFET is connected to the opposite phase of the clock signal;
p) wherein the drains of the first PFET and third PFET and the source of the second PFET are connected to the first output of the low-pass filter;
q) wherein the drains of the second NFET and third NFET and the source of the first NFET are connected to the second output of the low-pass filter.
9. The latch as in claim 8 wherein the inverter comprises:
a) a PFET, the PFET having a gate, drain, and source;
b) an NFET, the NFET having a gate, drain, and source;
c) wherein the gates of the PFET and NFET are connected to the input of the inverter;
d) wherein the drains of the PFET and NFET are connected to the output of the inverter;
e) wherein the source of the PFET is connected to VDD;
f) wherein the source of the NFET is connected to GND.
10. The latch as in claim 6 wherein the feedback keeper comprises:
a) a PFET, the PFET having a gate, drain, and source;
b) an NFET, the NFET having a gate, drain, and source;
c) wherein the gate of the PFET is connected to the first input of the feedback keeper;
d) wherein the gate of the NFET is connected to the second input of the feedback keeper;
e) wherein the drains of the PFET and NFET are connected to the output of the feedback keeper;
f) wherein the source of the PFET is connected to VDD;
g) wherein the source of the NFET is connected to GND.
11. A computer system, comprising:
a) at least one integrated circuit;
b) wherein at least one integrated circuit contains a latch;
c) wherein the latch comprises a forward inverter, a low-pass filter, and a feedback keeper;
d) such that the only type of diffusion attached to a first output of the low-pass filter is a P-type diffusion;
e) such that the only type of diffusion attached to a second output of the low-pass filter is an N-type diffusion.
12. The computer system as in claim 11 wherein the forward inverter comprises:
a) a PFET, the PFET having a gate, drain, and source;
b) an NFET, the NFET having a gate, drain, and source;
c) wherein the gates of the PFET and NFET are connected to the input of the forward inverter;
d) wherein the drains of the PFET and NFET are connected to the output of the forward inverter;
e) wherein the source of the PFET is connected to VDD;
f) wherein the source of the NFET is connected to GND.
13. The computer system as in claim 11 wherein the low-pass filter comprises:
a) a inverter, the inverter having an input and an output;
b) a first PFET, the first PFET having a gate, drain, and source;
c) a second PFET, the second PFET having a gate, drain, and source;
d) a third PFET, the third PFET having a gate, drain, and source;
e) a first NFET, the first NFET having a gate, drain, and source;
f) a second NFET, the second NFET having a gate, drain, and source;
g) a third NFET, the third NFET having a gate, drain, and source;
h) wherein the input of the low-pass filter is connected to the input of the inverter and the gates of the second PFET and the first NFET;
i) wherein the output of the inverter is connected to the gates of the first PFET and the second NFET;
j) wherein the sources of the first PFET, and the third PFET are connected to VDD;
k) wherein the drain of the first NFET is connected to VDD;
l) wherein the sources of the second NFET, and the third NFET are connected to GND;
m) wherein the drain of the second PFET is connected to GND;
n) wherein the gate of the third NFET is connected to a clock signal;
o) wherein the gate of the third PFET is connected to the opposite phase of the clock signal;
p) wherein the drains of the first PFET and third PFET and the source of the second PFET are connected to the first output of the low-pass filter;
q) wherein the drains of the second NFET and third NFET and the source of the first NFET are connected to the second output of the low-pass filter.
14. The computer system as in claim 13 wherein the inverter comprises:
a) a PFET, the PFET having a gate, drain, and source;
b) an NFET, the NFET having a gate, drain, and source;
c) wherein the gates of the PFET and NFET are connected to the input of the inverter;
d) wherein the drains of the PFET and NFET are connected to the output of the inverter;
e) wherein the source of the PFET is connected to VDD;
f) wherein the source of the NFET is connected to GND.
15. The computer system as in claim 11 wherein the feedback keeper comprises:
a) a PFET, the PFET having a gate, drain, and source;
b) an NFET, the NFET having a gate, drain, and source;
c) wherein the gate of the PFET is connected to the first input of the feedback keeper;
d) wherein the gate of the NFET is connected to the second input of the feedback keeper;
e) wherein the drains of the PFET and NFET are connected to the output of the feedback keeper;
f) wherein the source of the PFET is connected to VDD;
g) wherein the source of the NFET is connected to GND.
16. A latch for reducing soft errors comprising:
a) a means for inverting a signal, the means for inverting a signal having an input and an output;
b) a means for maintaining a logical value on a node, the means for maintaining a logical value on a node having a first input, a second input, and an output;
c) a means for filtering high frequency content from a signal, the means for filtering high frequency content from a signal having an input, a first output, and a second output;
d) such that the only type of diffusion attached to the first output of the means for filtering high frequency content from a signal is a P-type diffusion;
e) such that the only type of diffusion attached to the second output of the means for filtering high frequency content from a signal is an N-type diffusion;
f) wherein the output of the means for inverting a signal is connected to the input of the means for filtering high frequency content from a signal;
g) wherein the first output of the means for filtering high frequency content from a signal is connected to the first input of the means for maintaining a logical value on a node;
h) wherein the second output of the means for filtering high frequency content from a signal is connected to the second input of the means for maintaining a logical value on a node;
i) wherein the output of the means for maintaining a logical value on a node is connected to the input of the means for inverting a signal.
17. A method of manufacturing a latch comprising:
a) connecting a low-pass filter between an output of a transfer gate and inputs of a feedback keeper;
b) connecting a first output of the low-pass filter to a first input of the feedback keeper;
c) connecting a second output of the low-pass filter to a second input of the feedback keeper;
d) such that the only type of diffusion attached to the first output of the low-pass filter is a P-type diffusion;
e) such that the only type of diffusion attached to the second output of the low-pass filter is an N-type diffusion;
f) wherein an output of the feedback keeper is connected to the output of the transfer gate.
18. A latch comprising:
a) a feedback keeper;
b) a low-pass filter;
c) wherein an input/output of the latch is connected to an input of the low-pass filter;
d) wherein a first output of the low-pass filter is connected to a first input of the feedback keeper;
e) such that the only type of diffusion attached to the first output of the low-pass filter is a P-type diffusion;
f) wherein a second output of the low-pass filter is connected to a second input of the feedback keeper;
g) such that the only type of diffusion attached to the second output of the low-pass filter is an N-type diffusion;
h) wherein an output of the feedback keeper is connected to the input/output of the latch.
19. A computer system, comprising:
a) at least one integrated circuit;
b) wherein at least one integrated circuit contains a latch;
c) wherein the latch comprises a low-pass filter, and a feedback keeper;
d) such that the only type of diffusion attached to a first output of the low-pass filter is a P-type diffusion;
e) such that the only type of diffusion attached to a second output of the low-pass filter is an N-type diffusion.