Systems and methods of accessing common registers in a multi-core processor
View Patent ↗Systems and methods for accessing common registers in a multi-core processor are disclosed. In an embodiment a method may comprise streaming at least one transaction from one of a plurality of processing cores in a core domain directly to a register domain. The method may also comprise reassembling the at least one streamed transaction in the register domain for data access operations at the common registers.
1. A method of accessing common registers in a register domain in a multi-core processor, comprising:
streaming at least one transaction from one of a plurality of processing cores in a core domain directly to a register domain, both the core domain and the register domain being different clock domains in the same multi-core processor;
determining if the at least one transaction is addressed to the common registers before staging the at least one transaction for the common registers; and
reassembling the at least one streamed transaction in the register domain for data access operations at the common registers.
2. The method of claim 1 further comprising arbitrating access to the common registers.
3. The method of claim 1 further comprising writing data in the at least one transaction to the common registers.
4. The method of claim 1 further comprising synchronizing the segments in the core domain for streaming to the register domain.
5. The method of claim 1 further comprising reading data identified in the at least one transaction from the common registers.
6. The method of claim 1 further comprising:
streaming segments of data read from the common registers in the register domain to the core domain; and
reassembling the segments into the data read from the common registers in the core domain.
7. The method of claim 6 further comprising synchronizing the segments of data read from the common registers for streaming to the register domain.