System and method for monitoring a power supply level
View Patent ↗A system and method are provided herein for monitoring the integrity of a power supply by monitoring a level of the power supply voltage supplied to one or more system components. The method, as described herein, includes setting a bit in a status register after the power supply level reaches a threshold level, and monitoring a state of the bit to determine if the power supply level has dropped below the threshold level. For example, the method may determine that the power supply level has dropped below the threshold level if the state of the bit changes from a set bit to a cleared bit. In addition, the system and method described herein may be used for detecting the occurrence of a power abnormality by providing additional resources/information about a power related event.
1. A method for monitoring a power supply voltage level supplied to a system, the method comprising:
setting a bit in a status register in response to the power supply voltage level reaching a threshold level;
monitoring a state of the bit stored within the status register for changes;
determining that the power supply voltage level has dropped below the threshold level, if the step of monitoring indicates that the state of the bit has changed from a set bit to a cleared bit; and
wherein the steps of setting, monitoring, and determining are performed by a user of the system for diagnostic purposes.
2. The method as recited in claim 1 , wherein prior to the step of setting the bit, the method further comprises:
monitoring an output signal generated by a power-on/reset (POR) circuit associated with the system; and
clearing the bit in the status register if the output signal comprises a first asserted power-on/reset signal indicating an initial power-on/reset of the system.
3. The method as recited in claim 2 , wherein the threshold level comprises a minimum power supply voltage level required for operating one or more components included within the system.
4. The method as recited in claim 2 , wherein the step of setting the bit is performed only if the output signal generated by the POR circuit comprises the first asserted power-on/reset signal followed by a deasserted power-on reset signal.
5. The method as recited in claim 4 , wherein the step of clearing the bit is performed by supplying the first asserted power-on/reset signal generated by the POR circuit to the status register.
6. The method as recited in claim 4 , wherein after the step of setting the bit, the method further comprises re-clearing the bit in the status register if a subsequent output signal generated by the POR circuit comprises a second asserted power-on/reset signal.
7. The method as recited in claim 6 , wherein the step of re-clearing the bit is performed by supplying the subsequent output signal generated by the POR circuit to the status register.
8. The method as recited in claim 1 , wherein the step of monitoring a state of the bit is performed after the user is alerted to a problem with the system.
9. The method as recited in claim 1 , wherein the step of monitoring a state of the bit is performed according to predetermined time intervals selected from a group comprising random, periodic and continuous intervals, as defined by the user.
10. The method as recited in claim 1 , further comprising determining by the user that a power abnormality has occurred if the state of the bit changes from the set bit to the cleared bit.
11. A system for monitoring a power supply voltage level, the system comprising:
a power-on/reset (POR) circuit configured for generating a reset signal once the power supply voltage level begins ramping up towards a threshold voltage level, and deasserting the reset signal upon reaching the threshold voltage level;
a status register configured for storing a bit, having a first logic state, in response to the deasserted reset signal; and
a means for enabling a user of the system to monitor the stored bit and determine that the power supply voltage level has dropped below the threshold voltage level if the stored bit changes from the first logic state to a second logic state, different from the first.
12. The system as recited in claim 11 , wherein the bit having the first logic state is stored within the status register by a user of the system after the reset signal is deasserted by the POR circuit.
13. The system as recited in claim 11 , wherein the bit having the first logic state is stored within the status register by supplying the deasserted reset signal generated by the POR circuit to the status register.
14. The system as recited in claim 11 , wherein the status register is configured for storing the bit, having the second logic state, if the POR circuit generates a subsequent reset signal in response to the power supply voltage level dropping and then ramping back up towards the threshold voltage level.
15. The system as recited in claim 11 , where said means for enabling the user of the system to monitor the stored bit and determine that the power supply voltage level has dropped below the threshold voltage level is selected from a group comprising:
hardware-implemented logic located internal to the system and having access to the stored bit via a bus; and
software-implemented logic stored as program instructions on a computer-readable medium and executed by a processor of the system, wherein the system processor has access to the stored bit via the bus; and
wherein the hardware and software implemented logic are accessible to the user.
16. The system as recited in claim 15 , where the status register comprises an I2C register and the bus comprises an I2C bus.
17. The system as recited in claim 16 , wherein the hardware-implemented logic comprises an I2C controller.
18. The system as recited in claim 15 , wherein the status register comprises a register and the bus comprises a serial or parallel bus.