Fractional divider system and method

1. A fractional divider system for a low-power timer with reduced timing error at wake-up from a low power mode, comprising:

a fractional divider circuit configured to produce an output signal with a frequency F C with the following relation to a reference clock having a reference clock frequency F LP :

F

LP

=

(

M

+

N

P

DIV

)

⁢

⁢

F

c

wherein P DIV is a period of the fractional divider circuit, M is an integer part of a division ratio associated therewith, and N is the magnitude of a fractional part of the division ratio;

a high speed crystal oscillator circuit connected to the fractional divider circuit and configured to start and generate a high speed clock signal based on a wake-up from the low power mode;

a high speed clock divider circuit connected to the fractional divider circuit and to the high speed crystal oscillator circuit,

wherein the high speed crystal oscillator circuit is further configured to sample the output signal and a current state of a total timing error associated with the fractional divider circuit using the high speed clock signal, and

wherein the sampled output signal triggers the high speed clock divider circuit, and the sampled current state of the total timing error preloads the high speed clock divider circuit, and wherein the high speed clock divider circuit is further configured to synchronize a first pulse of the output clock signal to an ideal clock timing associated with an external reference clock to an accuracy within 1.5 periods of the high speed clock signal using the preloaded total timing signal.

2. The fractional divider system of claim 1 , wherein the fractional divider circuit comprises an accumulator circuit configured to account for the total timing error associated with the fractional divider circuit, and wherein the fractional divider system further comprises a counter configured to count a number of high-speed clock periods between the ideal timing reference to the first pulse of the output clock signal, thereby measuring the timing error.

3. The fractional divider system of claim 2 , wherein the accumulator circuit is configured to adjust the preload value for the high speed clock divider circuit upon leaving the low-power mode using the measured timing error from the counter.

4. The fractional divider system of claim 1 , wherein the fractional divider system further comprises a wake-up timer connected to the high speed crystal oscillator circuit, and configured to activate and thus bring the fractional divider system out of the low power mode, either due to an expiration of a time identified by the wake-up timer or due to an external signal requesting that the fractional divider system wake up identified by the wake-up timer.

5. The fractional divider system of claim 1 , wherein the fractional divider circuit further comprises an integer divider circuit connected to the wake-up timer circuit, and configured to divide the reference clock with an integer division ratio of either M or M+1.

6. The fractional divider system of claim 5 , wherein the fractional divider circuit further comprises a ratio selector means connected to the integer divider circuit, and configured to minimize the total timing error associated with the fractional divider circuit and keep such total timing error positive.

7. The fractional divider system of claim 2 , wherein a current timing error value stored in the accumulator circuit is denoted k, and wherein the number of cycles of the high speed clock required for the value k is given as:

n

HS

=

k

⁢

T

LP

P

DIV

⁢

T

HS

wherein T LP is the time period for the reference clock, and T HS is the time period for the high speed crystal oscillator circuit, with the values T LP , T HS and P DIV chosen such that a number of high speed clock cycles required is an integer multiple of the value k.

8. The fractional divider system of claim 7 , wherein the fractional divider system further comprises a first synchronizer circuit connected to the accumulator circuit, the high speed crystal oscillator circuit, and the high speed clock divider circuit, wherein the first synchronizer circuit is configured to output the preload value to the high speed clock divider circuit at a predetermined time.

9. The fractional divider system of claim 8 , wherein the fractional divider system further comprises a second synchronizer circuit connected to the integer divider circuit, the high speed crystal oscillator circuit, and the high speed clock divider circuit, wherein the second synchronizer circuit is configured to trigger the high speed clock divider circuit at a predetermined time.

10. The fractional divider system of claim 9 , wherein the fractional divider circuit also comprises an adder connected to the accumulator circuit, a subtractor connected to the accumulator circuit, and a multiplexer circuit connected to the adder, the subtractor and the ratio selector circuit, wherein the output from the multiplexer circuit is input to the accumulator circuit.

11. A method for reducing timing error at wake-up for a low-power timer comprising a fractional divider circuit, comprising:

producing an output signal with the fractional divider circuit with a frequency F C with the following relation to a reference clock signal having a reference clock frequency F LP ;

F

LP

=

(

M

+

N

P

DIV

)

⁢

⁢

F

C

wherein P DIV is a period of the fractional divider circuit, M is an integer part of the division ratio, and N is a magnitude of the fractional part of the division ratio;

sampling the output signal with a high speed clock associated with a high speed oscillator circuit;

sampling a current state of a total timing error associated with the fractional divider circuit with the high speed oscillator circuit;

triggering a high speed clock divider circuit with the sampled output signal;

preloading the high speed clock divider circuit with the sampled current state of the total timing error; and

synchronizing a first pulse of an output clock signal to an ideal clock timing of an external clock signal to an accuracy within 1.5 periods of the high speed clock using the preloaded state of the timing error.

12. The method of claim 11 , further comprising:

counting a number of clock periods of the high speed clock between the ideal timing reference to the first pulse of the output clock signal; and

adjusting the preload value based on the counted periods.

13. The method of claim 12 , further comprising:

exiting a low power mode of the timer, either due to an expiration of a wake-up timer, or due to an external signal requesting wake up; and

initiating the sampling in response to the exiting the lwo power mode.

14. The method of claim 13 , further comprising dividing the reference clock with an integer division ratio of either M or M+1.

15. The method of claim 14 , further comprising selecting an integer division ratio to divide such that a resultant timing error is minimized and remains positive.

16. The method of claims 11 , wherein a current timing error is denoted k, and wherein a number of cycles of the high speed clock required for the value k is given as:

n

HS

=

k

⁢

T

LP

P

DIV

⁢

T

HS

wherein T LP is the time period of the output signal, and T HS is the time period for the high speed crystal oscillator circuit, with the values T LP , T HS and P DIV chosen such that the number of high speed clock cycles required is an integer multiple of the value k.