System, method, and apparatus for pause and picture advance

1 . A method for displaying pictures, said method comprising:

displaying a first picture at a first vertical synchronization signal;

receiving a particular input between the first vertical synchronization signal and a second vertical synchronization signal, the second vertical synchronization signal coming after the first vertical synchronization signal;

displaying a second picture at the second vertical synchronization signal; and

preventing overwriting of the second picture.

2 . The method of claim 1 , further comprising preventing video decoding.

3 . The method of claim 2 , further comprising:

receiving another particular input between a third vertical synchronization signal and a fourth vertical synchronization signal, the fourth vertical synchronization signal coming after the third vertical synchronization signal;

displaying the second picture at the fourth vertical synchronization signal;

decoding at least one picture; and

displaying a third picture at a fifth vertical synchronization signal.

4 . The method of claim 3 , further comprising displaying the third picture at a sixth vertical synchronization signal.

5 . The method of claim 3 , further comprising:

preventing overwriting of the third picture.

6 . The method of claim 5 , further comprising preventing video decoding after decoding one picture.

7 . A system for displaying images on a display, said system comprising:

a first processor for displaying a first picture at a first vertical synchronization signal and displaying a second picture at a second vertical synchronization signal, the second vertical synchronization signal coming after the first vertical synchronization signal; and

a second processor for receiving a particular input between the first vertical synchronization signal and the second vertical synchronization signal and preventing the first processor from overwriting of the second picture.

8 . The system of claim 7 , wherein the second processor prevents the first processor from video decoding.

9 . The system of claim 8 , wherein the second processor receives another particular input between a third vertical synchronization signal and a fourth vertical synchronization signal, the fourth vertical synchronization signal coming after the third vertical synchronization signal, and wherein the first processor displays the second picture at the fourth vertical signal, decodes at least one picture and displays a third picture at a fifth vertical synchronization signal.

10 . The system of claim 9 , wherein the first processor displays the third picture at a sixth vertical synchronization signal.

11 . The system of claim 9 , wherein the second processor prevents the first processor from preventing overwriting of the third picture.

12 . The system of claim 11 , wherein the second processor prevents the first processor from video decoding after decoding one picture.

13 . A circuit for displaying pictures, said circuit comprising memory, said memory storing a plurality of executable instructions, said executable instructions for:

displaying a first picture at a first vertical synchronization signal;

receiving a particular input between the first vertical synchronization signal and a second vertical synchronization signal, the second vertical synchronization signal coming after the first vertical synchronization signal;

displaying a second picture at the second vertical synchronization signal; and

preventing overwriting of the second picture.

14 . The circuit of claim 13 , wherein the memory stores a plurality of executable instructions for preventing video decoding.

15 . The circuit of claim 14 , wherein the memory stores a plurality of executable instructions for:

receiving another particular input between a third vertical synchronization signal and a fourth vertical synchronization signal, the fourth vertical synchronization signal coming after the third vertical synchronization signal;

displaying the second picture at the fourth vertical synchronization signal;

decoding at least one picture; and

displaying a third picture at a fifth vertical synchronization signal.

16 . The circuit of claim 15 , wherein the memory stores a plurality of executable instructions for displaying the third picture at a sixth vertical synchronization signal.

17 . The circuit of claim 15 , wherein the memory stores a plurality of executable instructions for preventing overwriting of the third picture.

18 . The circuit of claim 17 , wherein the memory stores a plurality of executable instructions for preventing video decoding after decoding one picture.