Active socket for facilitating proximity communication

1. A computer system, comprising:

a processor;

a memory;

a substrate having an active face upon which active circuitry and signal pads reside, and a back face opposite the active face; an integrated circuit chip having an active face upon which active circuitry and signal pads reside, and a back face opposite the active face; wherein the integrated circuit chip is pressed against the substrate such that the active face of the integrated circuit chip is parallel to and adjacent to the active face of the substrate; wherein capacitive signal pads on the active face of the integrated circuit chip overlap signal pads on the active face of the substrate;

wherein at least one signal pad on the active face of the substrate is electrically coupled to a non-adjacent signal pad on the active face of the substrate, wherein the non-adjacent signal pad overlaps a signal pad on an active face of a third integrated circuit chip that is non-adjacent to the integrated circuit chip, thereby allowing the integrated circuit chip to communicate with the third integrated circuit chip; and whereby the integrated circuit chip and the substrate communicate with each other through capacitive coupling via the overlapping signal pads.

2. The computer system of claim 1 , further comprising:

a second integrated circuit chip having an active face upon which active circuitry and signal pads reside, and a back face opposite the active face;

wherein the second integrated circuit chip is pressed against the substrate such that the active face of the second integrated circuit chip is parallel to and adjacent to the active face of the substrate;

wherein capacitive signal pads on the active face of the second integrated circuit chip overlap signal pads on the active face of the substrate; and

whereby the second integrated circuit chip and the substrate communicate with each other through capacitive coupling via the overlapping signal pads.

3. The computer system of claim 2 , wherein a signal pad on the active face of the substrate overlaps a signal pad on the active face of the integrated circuit chip and also a signal pad on the active face of the second integrated circuit chip, thereby enabling the integrated circuit chip to communicate with the second integrated circuit chip.

4. The computer system of claim 1 , wherein the substrate includes a recessed cavity which is shaped so that the integrated circuit chip fits into the recessed cavity, thereby facilitating alignment in a plane parallel to the surface of the substrate, whereby the cavity eliminates alignment errors on the X, Y, and θ axis.

5. The computer system of claim 1 , wherein the substrate includes posts on the active side of the substrate configured so that the integrated circuit chip fits into a cavity defined by the posts thereby facilitating alignment in a plane parallel to the surface of the substrate, whereby the cavity eliminates alignment errors on the X, Y, and θ axis.

6. The computer system of claim 1 , wherein the substrate includes:

posts on the active side of the substrate configured so that the posts define two sides of a cavity on the active side of the substrate; and

MEMS springs on the active side of the substrate that press the integrated circuit chip into the cavity defined by the posts, thereby facilitating alignment in a plane parallel to the surface of the substrate, whereby the cavity eliminates alignment errors on the X, Y, and θ axis.

7. The computer system of claim 1 , wherein the processor and the memory are comprised of integrated circuit chips that are pressed against the substrate.

8. An apparatus for facilitating capacitive communication between integrated circuit chips, comprising: a substrate having an active face upon which active circuitry and signal pads reside, and a back face opposite the active face; an integrated circuit chip having an active face upon which active circuitry and signal pads reside, and a back face opposite the active face;

wherein the integrated circuit chip is pressed against the substrate such that the active face of the integrated circuit chip is parallel to and adjacent to the active face of the substrate; wherein capacitive signal pads on the active face of the integrated circuit chip overlap signal pads on the active face of the substrate; and

wherein at least one signal pad on the active face of the substrate is electrically coupled to a non-adjacent signal pad on the active face of the substrate, wherein the non-adjacent signal pad overlaps a signal pad on an active face of a third integrated circuit chip that is non-adjacent to the integrated circuit chip, thereby allowing the integrated circuit chip to communicate with the third integrated circuit chip; and whereby the integrated circuit chip and the substrate communicate with each other through capacitive coupling via the overlapping signal pads.

9. The apparatus of claim 8 , further comprising:

a second integrated circuit chip having an active face upon which active circuitry and signal pads reside, and a back face opposite the active face;

wherein the second integrated circuit chip is pressed against the substrate such that the active face of the second integrated circuit chip is parallel to and adjacent to the active face of the substrate;

wherein capacitive signal pads on the active face of the second integrated circuit chip overlap signal pads on the active face of the substrate; and

whereby the second integrated circuit chip and the substrate communicate with each other through capacitive coupling via the overlapping signal pads.

10. The apparatus of claim 9 , wherein a signal pad on the active face of the substrate overlaps a signal pad on the active face of the integrated circuit chip and also a signal pad on the active face of the second integrated circuit chip, thereby enabling the integrated circuit chip to communicate with the second integrated circuit chip.

11. The apparatus of claim 8 , wherein the substrate includes a recessed cavity which is shaped so that the integrated circuit chip fits into the recessed cavity, thereby facilitating alignment in a plane parallel to the surface of the substrate, whereby the cavity eliminates alignment errors on the X, Y, and θ axis.

12. The apparatus of claim 8 , wherein the substrate includes posts on the active side of the substrate configured so that the integrated circuit chip fits into a cavity defined by the posts thereby facilitating alignment in a plane parallel to the surface of the substrate, whereby the cavity eliminates alignment errors on the X, Y, and θ axis.

13. The apparatus of claim 8 , wherein the substrate includes:

posts on the active side of the substrate configured so that the posts define two sides of a cavity on the active side of the substrate; and

MEMS springs on the active side of the substrate that press the integrated circuit chip into the cavity defined by the posts, thereby facilitating alignment in a plane parallel to the surface of the substrate, whereby the cavity eliminates alignment errors on the X, Y, and θ axis.

14. The apparatus of claim 8 , wherein the integrated circuit chip can include one of a memory and a processor.