Error detection and correction for encoded data
View Patent ↗Embodiments of the present invention provide techniques for detecting and correcting encoded data. In one embodiment, a system for detecting and correcting errors in a plurality of data bits comprises a static memory configured to store a plurality of data bits; a systematic encoder configured to convert the plurality of data bits into a codeword; a systematic parity check encoder configured to convert the codeword into a syndrome; and a syndrome decoder configured to evaluate the syndrome based on preset criteria used to determine whether the syndrome corresponds to an uncorrectable error. A binary [16, 8, 5] code is used to encode the plurality of data bits.
1. A system for detecting and correcting errors in a plurality of data bits, the system comprising:
a memory configured to store a plurality of data bits;
a systematic encoder configured to convert the plurality of data bits stored in memory into a codeword;
a systematic parity check encoder configured to convert the codeword received from the systematic encoder into a syndrome; and
a syndrome decoder configured to evaluate the syndrome by directly mapping the syndrome to a plurality of acceptable syndrome sequences from a plurality of look up tables, wherein the plurality of lookup tables correspond to acceptable error patterns used to determine whether the syndrome corresponds to an uncorrectable error and include a first lookup table, a second lookup table, and a third lookup table,
wherein a binary [16, 8, 5] code is used to encode the plurality of data bits;
wherein the systematic encoder is configured to convert 8 data bits into a 16-bit codeword; and
wherein evaluation of the syndrome by the syndrome decoder includes the steps:
a) determine there are no errors if the syndrome consists of all zeros;
b) determine that a 1-data bit error exists if the syndrome is found in the first look up table stored in memory;
c) determine that a 1-check bit error exists if the syndrome is found in the second lookup table stored in memory;
d) determine that a 2 check bit error exists if the syndrome is found in the third lookup table stored in memory; and
e) determine that syndrome corresponds to an uncorrectable error if the syndrome is not in any of the plurality of lookup tables.
2. The system of claim 1 wherein the memory comprises DRAM or flash memory.
3. A hard disk controller comprising the system of claim 1 .
4. The hard disk controller of claim 3 wherein the plurality of data bits comprise non-customer data.
5. A hard disk drive comprising the hard disk controller of claim 3 .
6. The system of claim 1 wherein the memory, the systematic encoder, the systematic parity check encoder, and the syndrome encoder are provided in an integrated circuit.