IP Library Granted Patent US 7,459,786
Granted Patent B2
US 7,459,786 · App. 11/155,272 · Granted Dec 2, 2008

Semiconductor device

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Quick Facts
Patent No.
US 7,459,786
App. No.
11/155,272
Granted
Dec 2, 2008
Kind
B2
Abstract

A reliable semiconductor device having a multilayer wiring structure formed of copper as a main component material, which constrains occurrence of voids caused by stress migration. In the multilayer wiring structure, a first insulation layer having a high barrier property and a compression stress, and making contact with the upper surface of a first wiring made of copper as a main component material, a second insulation film having a tensile stress, and a third insulation film having a dielectric constant which is lower than those of the first and second insulation film, are laminated one upon another in the mentioned order as viewed the bottom thereof, and a via hole is formed piercing through the first insulation film, the second insulation film and the third insulation film, making contact with the first wiring.

Claims (24)

1. A semiconductor device comprising:

a first wiring formed on a semiconductor substrate through the intermediary of an insulation film and made of copper as a main component material,

a first insulation film formed on the first wiring and having a barrier property against the copper of the first wiring, the first film having a compressive stress,

a second insulation film formed on the first insulation film, and having a tensile stress,

a third insulation film formed on the second insulation film, and having a tensile stress,

a via formed on the first wiring and piercing through the third to the first insulation films, and

a second wiring connected to the first wiring through the intermediary of the via,

wherein the third insulation film has a dielectric constant which is lower than those of the first and second insulation films.

2. A semiconductor device as set forth in claim 1 , wherein

the first insulation film has a film thickness which is less than that of the second insulation film.

3. A semiconductor device as set forth in claim 1 , wherein

the first insulation film has a Yong's modulus which is larger than that of the second insulation film, but the first insulation film has a film thickness which is less than that of the second insulation film.

4. A semiconductor device as set forth in claim 1 , wherein

the second insulation film has a barrier property which is higher than that of a silicon oxide film, against copper of the first wiring.

5. A semiconductor device as set forth in claim 1 , wherein

the first insulation film is formed of an insulation film containing at least nitrogen atoms.

6. A semiconductor device as set forth in claim 1 , wherein

the third insulation film is a low dielectric insulation film.

7. A semiconductor device as set forth in claim 1 , wherein

an layer made of copper at least a part of which is nitrated is interposed between the first wiring and the first insulation film.

8. A semiconductor device as set forth in claim 7 , wherein

the layer made of copper at least a part of which is nitrated, has a film thickness which is less than that of the first insulation film.

9. A semiconductor device as set forth in claim 1 , wherein a space is formed at least a part of the third insulation film.

10. A semiconductor device as set forth in claim 9 , wherein the space is adjacent to a side wall of the via.