Memory controller controlling cashed DRAM
View Patent ↗According to the semiconductor device and method of the present invention, because regular cache memories subjected to hit checks are distinguished from spare cache memories not subjected to hit checks, and because sense amplifiers are also used as cache memories, built-in cache memories are operated faster and at low power consumption. A memory control unit is capable of distinguishing regular memories subjected to hit checks and spare memories not subjected to hit checks. This way, if a hit check is a miss, one of the cache memories not subjected to a hit checks is subjected to a subsequent hit operation and another one of the cache memories not subjected to hit checks is not subjected to the next hit check operation.
1. A memory controlling method for an information processing system having a CPU, a memory controller being supplied a read request from the CPU, and a memory unit controlled by the memory controller and being provided with a memory bank and a plurality of cache memories allocated against the memory bank, one of the plurality of cache memories being not subiect to a hit check operation, the method comprising the steps of:
reading out data from the memory bank to the one of the plurality of cache memories which is not subject to the hit check operation;
writing back data stored in another one of the plurality of cache memories which is subject to the hit check operation to the memory bank; and
changing the one of the plurality of cache memories which is not subject to the hit check operation so as to be subject to the hit check operation and the another one of the plurality of cache memories which is subject to the hit check operation so as to be not subject to the hit check operation.
2. A memory controlling method according to claim 1 , wherein the memory bank is a non-volatile memory.
3. A memory controlling method according to claim 1 , wherein the plurality of cache memories are non-volatile memories.
4. A memory controlling method according to claim 1 , wherein the plurality of cache memories are volatile memories.
5. A memory controlling method for an information processing system having a plurality of cache memories allocated against a memory bank wherein a first cache memory of the plurality of cache memories is in a first status in which the first cache memory acts as a spare cache memory and is not subject to a hit check operation and a second cache memory of the plurality of cache memories is in a second status in which the second cache memory is subject to a hit check operation, the method comprising the steps of:
reading out data from the memory bank to the first cache memory in the first status,
writing back data from the second cache memory in the second status to the memory bank,
changing the status of the first cache memory from the first status to the second status and changing the status of the second cache memory from the second status to the first status so that the second cache memory acts as the spare cache memory.
6. A memory controlling method according to claim 5 , wherein the memory bank is a non-volatile memory.
7. A memory controlling method according to claim 5 , wherein the plurality of cache memories are non-volatile memories.
8. A memory controlling method according to claim 5 , wherein the plurality of cache memories are volatile memories.
9. In an information processing system having a plurality of cache memories allocated against a memory bank, a method comprising the steps of:
providing a first cache memory in a first status in which the first cache memory acts as a spare cache memory which is not subject to a hit check operation;
providing a second cache memory in a second status in which the second cache memory is subject to a hit check operation;
reading out data from the memory bank to the first cache memory;
writing back data from the second cache memory to the memory bank; and
changing the status of the first cache memory from the first status to the second status and changing the status of the second cache memory from the second status to the first status so that the second cache memory acts as the spare cache memory.
10. The method according to claim 9 , wherein the step of writing is performed after the step of reading.
11. A memory controlling method according to claim 9 , wherein the memory bank is a non-volatile memory.
12. A memory controlling method according to claim 9 , wherein the plurality of cache memories are non-volatile memories.
13. A memory controlling method according to claim 9 , wherein the plurality of cache memories are volatile memories.