Method of fabricating a thin film transistor array substrate
View Patent ↗A thin film transistor array substrate and a fabricating method for simplifying a process and reducing a manufacturing cost. In the thin film transistor array substrate, a gate line is formed on a substrate and a gate insulating film is formed on the gate line. A data line is provided in such a manner to intersect the gate line with having the gate insulating film therebetween, and contains any at least one of tungsten silicide (WSi x ), cobalt silicide (CoSi x ) and nickel silicide (NiSi x ). A thin film transistor is provided at each intersection between the gate line and the data line. A pixel electrode is provided at a pixel area defined by each intersection between the gate line and the data line and is connected to the thin film transistor.
1. A method of fabricating a thin film transistor array substrate, the method comprising:
forming a gate pattern including a gate line and a gate electrode on a substrate;
forming a gate insulating film, an amorphous silicon layer and an n + amorphous silicon layer on the substrate provided with the gate pattern, and forming a source/drain metal layer containing at least one material of tungsten silicide (WSi x ), cobalt silicide (CoSi x ) or nickel silicide (NiSi x );
wherein the gate pattern, the gate insulating film, the amorphous silicon layers, and the source/drain metal layers are all formed by PECVD or MOCVD without removing the substrate from a processing environment in which the chemical vapor deposition process occurs;
patterning the amorphous silicon layer, the n + amorphous silicon layer and the source/drain metal layer to provide a semiconductor pattern and a source/drain pattern including the data line, the source electrode and the drain electrode formed on the semiconductor pattern;
wherein patterning the amorphous silicon layer, the n + amorphous silicon layer and the source/drain metal layer include patterning the source/drain metal layer by wet etching process, simultaneously patterning the amorphous silicon layer and the n + amorphous silicon layer by dry etching process, removing a photo resist pattern by ashing process, forming the source electrode and the drain electrode by etching process;
forming a protective film having a contact hole exposing a portion of the drain electrode on the substrate provided with the source/drain pattern; and
forming a pixel electrode connected, via the contact hole, to the drain electrode.
2. The method as claimed in claim 1 , wherein forming the source/drain metal layer includes:
injecting reaction materials comprising WF 6 , SiH 4 and N 2 into a chamber at about 325 to 425° C.; and
forming a source/drain metal material containing the tungsten silicide (WSi x ) produced by a reaction of the reaction materials on the n + amorphous silicon layer.
3. The method as claimed in claim 2 , wherein forming the source/drain metal layer includes:
injecting reaction materials of Co(CO) 3 NO, SiH 4 and H 2 into a chamber at about 300 to 400° C.; and
forming a source/drain metal material containing the cobalt silicide (CoSi x ) produced by a reaction of the reaction materials on the n + amorphous silicon layer.
4. The method as claimed in claim 2 , wherein forming the source/drain metal layer includes:
forming a source/drain metal material containing the nickel silicide (NiSi x ) produced by making a phase-change of nickel (Ni) and silicon (Si) with respect to each other at about 200 to 300° C. on the n + amorphous silicon layer by MOCVD.
5. The method as claimed in claim 2 , further comprising:
providing a storage capacitor including the gate line, and a storage electrode overlapping the gate line with the gate insulating film and the semiconductor pattern therebetween and formed from the same material as the data line.