Granted Patent B1

US 7,356,650 · App. 11/156,225 · Granted Apr 8, 2008

Abstract

Claims (44)

1. A data processing system, comprising:

at least one processor that issues memory requests responsive to instruction execution, the memory requests including a first memory request;

a first-level cache coupled to the at least one processor, wherein the first-level cache bypasses storing data for the first memory request responsive to a do-not-cache attribute associated with the first memory request;

a second-level cache coupled to the first-level cache, wherein the second-level cache bypasses updating of least-recently-used indicators of the second-level cache responsive to the do-not-cache attribute associated with the first memory request and stores the data for the first memory request, wherein the second-level cache stores the data for the first memory request responsive to absence of a do-not-cache attribute associated with the first memory request, stores the data for the first memory request responsive to a mode for the second-level cache having a first value and independent of presence or absence of the do-not-cache attribute, and bypasses storing the data for the first memory request responsive to the do-not-cache attribute associated with the memory request and the mode for the second-level cache having a second value; and

a memory arrangement coupled to the second-level cache.

2. The data processing system of claim 1 , wherein the second-level cache stores the data for the first memory request at a location indicated as least recently accessed by the least-recently-used indicators.

3. The data processing system of claim 1 , wherein the second-level cache stores the data for the first memory request in a location in the second-level cache and updates the least-recently-used indicators indicating that the location is most recently accessed responsive to absence of a do-not-cache attribute associated with the first memory request.

4. The data processing system of claim 1 , wherein a size of a cache line of the first-level cache is different than a size of a cache line of the second-level cache.

5. The data processing system of claim 1 , wherein the first-level cache is a write-through cache and the second-level cache is a write-back cache.

6. The data processing system of claim 1 , wherein the second-level cache is at least 2-way set-associative and has a plurality of sets, each set having at least 2 tag-data pairs.

7. The data processing system of claim 6 , wherein the least-recently-used indicators of the second-level cache indicate for each set, one of the tag-data pairs in the set as least recently accessed.

8. The data processing system of claim 6 , wherein the first memory request is issued with an address for the data, and the second-level cache associates the address with one set of the plurality of sets and associates the address with a tag-data pair in the set.

9. The data processing system of claim 8 , wherein the second-level cache associates the address with the tag-data pair that is least recently accessed in the set responsive to absence of the data in the second-level cache.

10. The data processing system of claim 8 , wherein the second-level cache provides access to the data in the tag-data pair of the set responsive to presence of the data in the second-level cache.

11. The data processing system of claim 8 , wherein the second-level cache updates the least-recently-used indicators indicating that the tag-data pair of the set is most recently accessed responsive to absence of a do-not-cache attribute associated with the first memory request.

12. A cache arrangement for a data processing system, comprising:

a first level cache;

a second level cache coupled to the first level cache, the second-level cache including:

a storage arrangement having storage for a plurality of sets of tag-data pairs, wherein each set has at least two tag-data pairs, and each memory address of a plurality of memory addresses is associated with one of the sets of tag-data pairs;

a plurality of sets of replacement indicators respectively associated with the sets of tag-data pairs, and each set of replacement indicators specifying a replacement order for the associated set of tag-data pairs; and

cache control logic coupled to the storage arrangement and to the replacement indicators, wherein the cache control logic, responsive to absence of a do-not-cache attribute associated with a memory request, stores data indicative of a memory address of the memory request and data referenced by the memory address in one of the tag-data pairs of the set of tag-data pairs associated with the memory address, the one of the tag-data pairs indicated as first in the replacement order by the one of the sets of replacement indicators associated with the one of the tag-data pairs, and updates the one of the sets of replacement indicators indicating that the one of the tag-data pairs is last in the replacement order specified by the one of the sets of replacement indicators, and the cache control logic bypasses update of the one of the sets of replacement indicators and stores data referenced by the memory address in the one of the tag-data pairs, responsive to the do-not-cache attribute being associated with the memory request;

wherein the first level cache stores the data referenced by the memory address in response to absence of the do-not-cache attribute, and bypasses storing of the data referenced by the memory address in response to the do-not-cache attribute being associated with the memory request; and

a mode register coupled to the cache control logic, wherein the cache control logic stores the memory data for the memory request in the tag-data pair in the associated set responsive to the mode register having a first value and independent of presence or absence of the do-not-cache attribute, and bypasses storage of the memory data for the memory request in the tag-data pair in the associated set responsive to the do-not-cache attribute being associated with the memory request and the mode register having a second value.

13. The cache arrangement of claim 12 , wherein the cache control logic stores the memory data for the memory request in the tag-data pair in the associated set.

14. The cache arrangement of claim 12 , wherein, for the memory request with write data to write to the memory address, the cache control logic updates with the write data a portion of the tag-data pair associated with the memory address in the set associated with the memory address.

15. A method for accessing a memory address in a computing system, comprising

issuing from a requester a read request for data at the memory address;

providing the data for the read request to the requester;

storing the data in a first-level cache in response to absence of a do-not-cache attribute associated with the read request;

bypassing storage of the data in the first-level cache in response to the do-not-cache attribute being associated with the read request;

storing the data in a set associative second-level cache, the second-level cache having a plurality of sets and each set including at least two tag-data pairs, wherein the data is stored in a set associated with the memory address and in a first tag-data pair of the set that is first in a replacement order of the tag-data pairs of the set;

adjusting the replacement order of the tag-data pairs in the set associated with the memory address in response to absence of a do-not-cache attribute associated with the read request, wherein the first tag-data pair is made last in the replacement order;

bypassing adjustment of the replacement order in response to the do-not-cache attribute being associated with the read request;

storing the data in the second-level cache responsive to absence of a do-not-cache attribute associated with the read request;

storing the data in the second-level cache responsive to a mode for the second-level cache having a first value and independent of presence or absence of the do-not-cache attribute; and

bypassing storing of the data in the second-level cache responsive to the do-not-cache attribute associated with the memory read and the mode for the second-level cache having a second value.

16. The method of claim 15 , wherein providing the data for the read request to the requester further comprises:

providing the data from the first-level cache in response to presence of the data in the first-level cache;

providing the data from the second-level cache in response to absence of the data in the first-level cache and presence of the data in the second-level cache; and

providing the data from a memory arrangement in response to absence of the data in the first-level cache and second-level cache.

17. The method of claim 15 , further comprising:

issuing from the requester a write request with update data to update the data at the memory address;

updating the first-level cache with the update data in response to presence of the data in the first-level cache; and

updating the second-level cache with the update data.

Assignments (13)