IP Library Granted Patent US 7,348,197
Granted Patent B2
US 7,348,197 · App. 11/158,000 · Granted Mar 25, 2008

Liquid crystal display device and fabrication method thereof

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Quick Facts
Patent No.
US 7,348,197
App. No.
11/158,000
Granted
Mar 25, 2008
Kind
B2
Abstract

A method for fabricating a liquid crystal display device includes providing first and second substrates; forming an active layer on the first substrate, wherein the active layer includes a source region, a drain region, a channel region, and a storage region; forming a first insulation layer on the first substrate; forming a gate electrode, a gate line, a pixel electrode, and a storage line on the first substrate, wherein storage line overlaps the storage region; forming a second insulation layer on the first substrate; forming first and second contact holes through the first and second insulation layers, wherein the first and second contact holes expose respective ones of the source and drain regions; forming a pixel hole through the second insulation layer, wherein the pixel hole exposes the pixel electrode; forming a source electrode electrically connected to the source region through the first contact hole and a drain electrode electrically connected to the drain region through the second contact hole; and forming a liquid crystal layer between the first and second substrates.

Claims (29)

1. A method for fabricating a liquid crystal display device, comprising:

forming an active layer on a first substrate, wherein the active layer includes a source region, a drain region, a channel region, and a storage region;

forming a first insulation layer on the first substrate;

forming a first and second conductive layers on the first substrate;

forming a gate electrode, a gate line, a pixel electrode, and a storage line on the first substrate by patterning the first and second conductive layers, wherein storage line overlaps the storage region;

forming a second insulation layer on the first substrate;

forming first and second contact holes through the first and second insulation layers, wherein the first and second contact holes expose respective ones of the source and drain regions;

opening the pixel electrode by removing the second insulation layer and a portion of the second conductive layer on the pixel electrode, wherein the gate electrode, the gate line, and the storage line include the first and second conductive layers, and wherein the pixel electrode includes the first conductive layer; and

forming a source electrode electrically connected to the source region through the first contact hole and a drain electrode electrically connected to the drain region through the second contact hole.

2. The method of claim 1 , wherein the active layer includes silicon.

3. The method of claim 2 , wherein the active layer includes polycrystalline silicon.

4. The method of claim 1 , wherein at least one of the first and second conductive layers includes a transparent conductive material.

5. The method of claim 4 , wherein the transparent conductive material includes at least one of indium tin oxide (ITO) and indium zinc oxide (IZO).

6. The method of claim 1 , wherein the second conductive layer includes an opaque conductive material.

7. The method of claim 6 , wherein the opaque conductive material includes at least one of aluminum, aluminum alloy, tungsten, copper, chromium, and molybdenum.

8. The method of claim 1 , wherein forming the first and second contact holes and opening the pixel electrode are substantially simultaneously preceded.

9. The method of claim 8 , wherein an area of the opened the pixel electrode is greater than or equal to the area of the pixel electrode.

10. The method of claim 9 , wherein the second insulation layer is patterned as the structure of the pixel electrode.

11. The method of claim 1 , wherein the storage region is between the gate line and the pixel electrode.

12. The method of claim 1 , wherein the storage region is parallel to the gate line.

13. The method of claim 1 , wherein the storage line partially overlaps the storage region.

14. The method of claim 1 , wherein the storage line is on the storage region and the first insulation layer is between the storage line and the storage region.

15. The method of claim 1 , further comprising implanting impurity ions into the active layer after forming the gate electrode and storage line to form the source and drain regions.

16. The method of claim 15 , wherein the impurity ions include at least one of a Group III and a Group V element.

17. The method of claim 16 , wherein the Group III element includes boron (B) and the Group V element includes phosphorous (P).

18. The method of claim 1 , wherein the source and drain regions include at least one of a p+ region and a n+ region.

19. The method of claim 1 , wherein forming the gate electrode, the gate line, the pixel electrode, and the storage line are substantially simultaneously preceded.

20. The method of claim 1 , wherein forming the gate line and the storage line are substantially simultaneously preceded.

21. The method of claim 1 , wherein forming the first and second contact holes and removing the second insulation layer on the pixel electrode are substantially simultaneously preceded.

Assignments (2)
CHANGE OF NAME Recorded Oct 17, 2008
From: LG.PHILIPS LCD CO., LTD.
To: LG DISPLAY CO., LTD.
Reel/Frame 021754/0045 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 22, 2005
From: PARK, YONG IN; LEE, DEA YUN
To: LG.PHILIPS LCD CO., LTD.
Reel/Frame 016711/0743 →