IP Library Granted Patent US 7,719,074
Granted Patent B2
US 7,719,074 · App. 11/159,571 · Granted May 18, 2010

Sensor die structure

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,719,074
App. No.
11/159,571
Granted
May 18, 2010
Kind
B2
Abstract

A sensor is implemented in an integrated circuit. The sensor includes one or more sensor pads that are provided at or near a surface of the integrated circuit. One or more integrated circuit components such as a sense amplifier are provided in the integrated circuit die adjacent the sensor pads. One or more other components are provided in the integrated circuit die adjacent the sensor pads.

Claims (28)

1. An integrated circuit comprising:

a plurality of sensor pads in at least one metal layer of the integrated circuit; and

a tile functional block replicated in a substrate layer of the integrated circuit directly beneath each of the plurality of sensor pads, respectively,

wherein the tile functional block includes a sensor component and an other component,

wherein the other components form at least one of a data memory and a programmable logic array.

2. The integrated circuit of claim 1 , comprising a plurality of components not located beneath the sensor pads and connected to at least one of the sensor components and the other components located beneath the sensor pads.

3. The integrated circuit of claim 1 , wherein the sensor components comprise sense amplifiers.

4. The integrated circuit of claim 1 , wherein at least a portion of the other components comprise boot ROM.

5. The integrated circuit of claim 1 , wherein at least a portion of the other components comprise one-time-programmable memory.

6. The integrated circuit of claim 1 , wherein at least a portion of the other components comprise RAM.

7. The integrated circuit of claim 1 , wherein the sensor pads comprise metal plates.

8. The integrated circuit of claim 1 , wherein the integrated circuit comprises a biometric sensor.

9. The integrated circuit of claim 1 , wherein the integrated circuit comprises a fingerprint reader.

10. A system on a chip implemented as an integrated circuit comprising:

at least one processor; and

a sensor comprising:

a plurality of sensor pads in at least one metal layer of the integrated circuit; and

a tile functional block replicated in a substrate layer of the integrated circuit directly beneath each of the plurality of sensor pads, respectively,

wherein the tile functional block includes a sensor component and an other component,

wherein the other components form at least one of a data memory and a programmable logic array.

11. The system of claim 10 , wherein the other components are coupled to the at least one processor.

12. The system of claim 10 , wherein the sensor components comprise sense amplifiers.

13. The system of claim 10 , comprising a plurality of other components not located beneath the sensor pads and connected to at least one of the sensor components and the other components located beneath the sensor pads.

14. The system of claim 10 , wherein the other components are coupled to the at least one processor and at least a portion of the other components comprise boot ROM.

15. The system of claim 10 , wherein the other components are coupled to the at least one processor and at least a portion of the other components comprise one-time-programmable memory.

16. The system of claim 10 , wherein the other components are coupled to the at least one processor and at least a portion of the other components comprise RAM.

17. The system of claim 10 , wherein the chip comprises a biometric sensor.

18. The system of claim 10 , wherein the chip comprises a fingerprint reader.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE PROPERTY NUMBERS PREVIOUSLY RECORDED AT REEL: 47630 FRAME: 344. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 21, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0267 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 9/5/2018 PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0687. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0344 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0687 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 13, 2005
From: BUER, MARK
To: BROADCOM CORPORATION
Reel/Frame 016790/0300 →