Magnetic random access memory array having bit/word lines for shared write select and read operations

1. A magnetic random access memory array, comprising:

a plurality of rows and columns of magnetic random access memory elements, the elements of each row having a word line and a write digit line and the elements of each column having a bit line and a write bit line;

a first selection circuit for each row having a first source-drain path coupled in the write digit line and a gate terminal coupled to the word line; and

a second selection circuit for each column having a second source-drain path coupling in the write bit line and a gate terminal coupled to the bit line.

2. The array of claim 1 further comprising:

a write driver circuit coupled to the word line; and

a word line select circuit coupled to the word line.

3. The array of claim 2 further comprising:

a multiplexer having first and second ports on a first side coupled to the write driver circuit and the word line select circuit, respectively, and a third port on a second side coupled to the word line.

4. The array of claim 3 further including a multiplexer selection signal coupled to the multiplexer for selectively connecting the first/second ports to the third port in response to a write/read signal.

5. The array of claim 4 wherein the write/read signal is derived from a write/read operational mode of the array.

6. The array of claim 1 further comprising:

a write driver circuit coupled to the bit line; and

a sense amplifier circuit coupled to the bit line.

7. The array of claim 6 further comprising:

a multiplexer having first and second ports on a first side coupled to the write driver circuit and the sense amplifier circuit, respectively, and a third port on a second side coupled to the bit.

8. The array of claim 7 further including a multiplexer selection signal coupled to the multiplexer for selectively connecting the first/second ports to the third port in response to a write/read signal.

9. The array of claim 8 wherein the write/read signal is derived from a write/read operational mode of the array.

10. The array of claim 1 further comprising:

a first write driver circuit coupled to the word line;

a word line select circuit coupled to the word line;

a second write driver circuit coupled to the bit line; and

a sense amplifier circuit coupled to the bit line.

11. The array of claim 10 , further comprising:

a first multiplexer having first and second ports on a first side coupled to the write driver circuit and the word line select circuit, respectively, and a third port on a second side coupled to the word line; and

a second multiplexer having first and second ports on a first side coupled to the write driver circuit and the sense amplifier circuit, respectively, and a third port on a second side coupled to the bit.

12. The array of claim 11 further comprising:

a first multiplexer selection signal coupled to the first multiplexer for selectively connecting the first/second ports to the third port in response to a first write/read signal; and

a second multiplexer selection signal coupled to the second multiplexer for selectively connecting the first/second ports to the third port in response to a second write/read signal.

13. The array of claim 12 wherein the first and second write/read signals are derived from a write/read operational mode of the array.

14. The array of claim 1 , wherein:

a first write signal applied to one word line actuates the first selection circuit for the row corresponding to that one word line and causes a write current to flow through the first source-drain path of the actuated first selection circuit and the corresponding write digit line to write data into certain memory elements in that row.

15. The array of claim 1 , wherein:

a second write signal applied to one bit line actuates the second selection circuit for the column corresponding to that one bit line and causes a write current to flow through the second source-drain path of the actuated second selection circuit and the corresponding write bit line to write data into at least one memory element in that column.

16. The array of claim 1 wherein each word line is a segmented word line comprised of a global word line and a plurality of local word lines.

17. The array of claim 1 wherein each write digit line is a segmented write digit line comprised of a global write digit line and a plurality of local write digit lines, the first selection circuit for selecting one of the local write digit lines.

18. The array of claim 1 wherein each word line is a segmented word line comprised of a global word line and a plurality of local word lines and wherein each write digit line is a segmented write digit line comprised of a global write digit line and a plurality of local write digit lines, the first selection circuit for selecting one of the local write digit lines.

19. The array of claim 1 wherein each bit line is a segmented bit line comprised of a global bit line and a plurality of local bit lines.

20. The array of claim 1 wherein each write bit line is a segmented write bit line comprised of a global write bit line and a plurality of local write bit lines, the second selection circuit for selecting one of the local write bit lines.

21. The array of claim 1 wherein each bit line is a segmented bit line comprised of a global bit line and a plurality of local bit lines and wherein each write bit line is a segmented write bit line comprised of a global write bit line and a plurality of local write bit lines, the second selection circuit for selecting one of the local write bit lines.

22. A magnetic random access memory array, comprising:

a plurality of rows and columns of magnetic random access memory elements, the elements of each row having a word line and a write digit line and the elements of each column having a bit line and a write bit line; and

a selection circuit for each column having a source-drain path coupled in the write bit line and a gate terminal coupled to the bit line.

23. The array of claim 22 further comprising:

a write driver circuit coupled to the bit line; and

a sense amplifier circuit coupled to the bit line.

24. The array of claim 23 further comprising:

a multiplexer having first and second ports on a first side coupled to the write driver circuit and the sense amplifier circuit, respectively, and a third port on a second side coupled to the bit line.

25. The array of claim 24 further including a multiplexer selection signal coupled to the multiplexer for selectively connecting the first/second ports to the third port in response to a write/read signal.

26. The array of claim 25 wherein the write/read signal is derived from a write/read operational mode of the array.

27. The array of claim 22 , wherein:

a write signal applied to one bit line actuates the selection circuit for the column corresponding to that one bit line and causes a write current to flow through the source-drain path of the actuated selection circuit and the corresponding write bit line to write data into certain memory elements in that column.

28. The array of claim 22 wherein the bit line is a segmented bit line comprised of a global bit line and a plurality of local bit lines.

29. The array of claim 22 wherein the write bit line is a segmented write bit line comprised of a global write bit line and a plurality of local write bit lines, the selection circuit for selecting one of the local write bit lines.

30. The array of claim 22 wherein the bit line is a segmented bit line comprised of a global bit line and a plurality of local bit lines and the write bit line is a segmented write bit line comprised of a global write bit line and a plurality of local write bit lines, the selection circuit for selecting one of the local write bit lines.