Regular routing for deep sub-micron chip design
View Patent ↗A method of routing an interconnect metal layer of an integrated circuit, wherein single-width nets are replicated and routed in parallel to reduce the total resistance on the net; wide wires are decomposed into a several single-width wires routed in parallel to improve uniformity of metal interconnect routing and therefore manufacturability of metal interconnect layers. The decomposition step is performed during a preliminary wire route after initial physical placement. Access to pin shapes is ensured through a branching and a recombination of the parallel single-width wires. Separate wire segments are rejoined at the source and sink of the net. The parallel wire segments do not change the logic behavior of the circuit.
1. A method of routing a metal interconnect layer in an integrated circuit, the method comprising:
defining a single-width wire having a width corresponding to a design ground rule minimum-width;
defining a wide wire having a width greater than the design ground rule minimum-width;
generating a net list from a logical design file;
performing a first interconnect routing of the metal interconnect layer based on an initial physical placement of a plurality of logic elements within the integrated circuit;
replicating a first single-width wire such that multiple instances of the first single-width wire are routed in parallel and terminated in accordance with a source and a sink as defined in the net list;
decomposing a first wide wire into a plurality of single-width wires such that a resistance through the plurality of single-width wires is substantially equal to a resistance through the first wide wire; and
iteratively routing the metal interconnect layer until a plurality of predefined design specifications are satisfied.
2. The method according to claim 1 , wherein the interconnect metal layer is routed with an off-grid router.
3. The method according to claim 1 , further comprising installing an automated software interconnect router on a distributed server system.
4. The method according to claim 1 , further comprising a plurality of wire widths.
5. The method according to claim 1 , wherein the replicating step is performed such that blockage shapes are not routed through and pin access is preserved.
6. The method according to claim 1 , further comprising a plurality of redundant vias between adjacent metal layers.
7. The method according to claim 1 , further comprising replicating a plurality of single width-wires.
8. The method according to claim 1 , further comprising decomposing a plurality of wide wires.
9. The method according to claim 1 , further comprising routing a plurality of interconnect metal layers.
10. The method according to claim 1 , further comprising terminating a first signal at a common source and a common sink as defined in the net list.
11. The method according to claim 1 , wherein the step of decomposing the first wide wire into a plurality of single-width wires is achieved without changing the logic behavior of the integrated circuit.
12. The method according to claim 1 , wherein a single-width wire is replicated, if it has an aspect ratio (length/width) greater than 10:1.
13. The method according to claim 1 , wherein a single width wire is replicated, if it has an aspect ratio (length/width) preferably greater than 100:1.
14. The method according to claim 1 , wherein a single-width wire is replicated, if it has an aspect ratio length/width preferably greater than 1000:1.
15. A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for implementing a voltage reference circuit, said method steps comprising:
defining a single-width wire corresponding to a design ground rule minimum-width;
defining a wide wire having a width greater than the design ground rule minimum-width;
generating a net list from a logical design file;
performing a first interconnect routing of the metal interconnect layer based on an initial physical placement of a plurality of logic elements within the integrated circuit;
replicating a first single-width wire such that multiple instances of the first single-width wire are routed in parallel and terminated in accordance with a source and a sink as defined in the net list;
decomposing a first wide wire into a plurality of single-width wires such that a resistance through the plurality of single-width wires is substantially equal to a resistance through the first wide wire; and
iteratively routing the metal interconnect layer until a plurality of predefined design specifications are satisfied.