IP Library Granted Patent US 7,468,760
Granted Patent B2
US 7,468,760 · App. 11/163,153 · Granted Dec 23, 2008

Apparatus and related method for level clamping control

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Quick Facts
Patent No.
US 7,468,760
App. No.
11/163,153
Granted
Dec 23, 2008
Kind
B2
Abstract

A level clamping control circuit and associated level clamping control method are provided. The level clamping control circuit includes a reference level estimator, a subtractor, a clamping computation circuit, a dithering circuit, and a digital-to-analog converter (DAC). The reference level estimator estimates a reference level of the input signal. The subtractor computes a difference between the reference level and a desired reference level to output a difference signal. The clamping computation circuit generates a first control value according to the difference signal. The dithering circuit dithers the first control value to alternately output a plurality of second control values. Finally, the DAC respectively utilizes the second control values to charge or discharge a capacitor to adjust the reference level of the input signal.

Claims (27)

1. A level clamping control circuit for clamping an input signal, comprising:

a reference level estimator for estimating a reference level of the input signal;

a subtractor, coupled to the reference level estimator, for computing a difference between the reference level and a desired reference level to output a difference signal;

a clamping computation circuit, coupled to the subtractor, for generating a first control value according to the difference signal;

a dithering circuit, coupled to the clamping computation circuit, for dithering the first control value to alternately output a plurality of second control values; and

a digital-to-analog converter (DAC), coupled to the dithering circuit and a capacitor, for generating an analog signal to alternatively charge and discharge the capacitor to adjust the reference level of the input signal according to the second control values.

2. The level clamping control circuit of claim 1 , wherein the DAC is a current-output DAC.

3. The level clamping control circuit of claim 1 , wherein before the reference level estimator estimates a new reference level of the input signal, the dithering circuit always keeps dithering the first control value, and the DAC always keeps charging or discharging the capacitor.

4. The level clamping control circuit of claim 1 , wherein the number of the second control values dithered from the first control value is two.

5. The level clamping control circuit of claim 1 , wherein the second control values are integers.

6. The level clamping control circuit of claim 1 , wherein the level clamping control circuit is implemented in a video decoder.

7. The level clamping control circuit of claim 1 , wherein the input signal is a composite video signal.

8. The level clamping control circuit of claim 7 , wherein the composite video signal complies with an NTSC (National Television System Committee) specification or a PAL (Phase Alternate Line) specification.

9. The level clamping control circuit of claim 7 , wherein the reference level indicates a blank level of the composite video signal.

10. A method for level clamping an input signal, comprising:

estimating a reference level of the input signal;

computing a difference between the reference level and a desired reference level to output a difference signal;

generating a first control value according to the difference signal;

dithering the first control value to alternately output a plurality of second control values; and

generating an analog signal to adjust the reference level of the input signal according to the second control values.

11. The method of claim 10 , wherein the number of the second control values dithered from the first control value is two.

12. The method of claim 10 , wherein the second control values are integers.

13. The method of claim 10 , wherein before estimating a new reference level of the input signal, the step of dithering the first control value always keeps dithering the first control value.

14. The method of claim 13 , wherein before estimating the new reference level of the input signal, the step of generating the analog signal always keeps charging or discharging a capacitor to adjust the reference level of the input signal.

15. The method of claim 10 , wherein the input signal is a composite video signal.

16. The method of claim 15 , wherein the composite video signal complies with an NTSC (National Television System Committee) specification or a PAL (Phase Alternate Line) specification.

17. The method of claim 15 , wherein the reference level indicates a blank level of the composite video signal.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 1, 2021
From: MEDIATEK INC.
To: XUESHAN TECHNOLOGIES INC.
Reel/Frame 055443/0818 →
MERGER Recorded Jun 12, 2020
From: MSTAR SEMICONDUCTOR, INC.
To: MEDIATEK INC.
Reel/Frame 052931/0468 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 6, 2005
From: HUANG, KE-CHIANG; KAO, TA-CHAN; SMITH, STERLING
To: MSTAR SEMICONDUCTOR, INC.
Reel/Frame 016626/0527 →