IP Library Granted Patent US 7,323,378
Granted Patent B2
US 7,323,378 · App. 11/163,472 · Granted Jan 29, 2008

Method for fabricating CMOS image sensor

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,323,378
App. No.
11/163,472
Granted
Jan 29, 2008
Kind
B2
Abstract

This invention provides a CMOS image sensor having a pinned photodiode. A P substrate is provided having thereon a P well. The P well is adjacent to a light-sensing region of the CMOS image sensor. A gate electrode of a transfer transistor of the CMOS image sensor is formed on the P well. A self-aligned implantation is performed to form N-type diode diffusion within the light-sensing region. An oblique ion implantation process is then performed to form N-type pocket diffusion directly under the gate electrode. Spacers are formed on sidewalls of the gate electrode. A surface P+ pinning diffusion region is then formed in the diode diffusion region.

Claims (23)

1. A method for fabricating a CMOS image sensor, comprising:

providing a semiconductor substrate of a first conductivity type, said semiconductor substrate including a light-sensing region;

forming a gate electrode of a transfer transistor of said CMOS image sensor on said semiconductor substrate, wherein an end portion of said gate electrode is adjacent to said light-sensing region;

performing a self-aligned ion implantation process to form a diode diffusion region of a second conductivity type in said semiconductor substrate within said light-sensing region;

performing an oblique ion implantation process to form a pocket diffusion region of said second conductivity type in said semiconductor substrate directly under said end portion of said gate electrode adjacent to said diode diffusion region;

forming a floating diffusion region of said second conductivity type in said semiconductor substrate, said floating diffusion region being disposed at a side of said gate electrode and space-apart from said pocket diffusion region;

after forming said diode diffusion region and said pocket diffusion region, forming spacers on sidewalls of said gate electrode; and

forming a surface pinning diffusion region of said first conductivity type in said diode diffusion region, wherein said surface pinning diffusion region, said diode diffusion region, said pocket diffusion region and said semiconductor substrate constitute a pinned photodiode.

2. The method according to claim 1 wherein prior to forming the gate electrode of the transfer transistor, the method further comprises the following step:

forming a diffusion well of said first conductivity type in said semiconductor substrate, said diffusion well being adjacent to said light-sensing region of said CMOS image sensor.

3. The method according to claim 1 wherein said self-aligned ion implantation process comprises the following steps:

forming a first photoresist layer on said semiconductor substrate, wherein said first photoresist layer has a first opening that exposes a portion of said light-sensing region and a portion of said gate electrode; and

implanting dopant species of said second conductivity type into said semiconductor substrate through said first opening, thereby forming said diode diffusion region.

4. The method according to claim 3 wherein said oblique ion implantation process comprises the following step:

obliquely implanting dopant species of said second conductivity type into said semiconductor substrate through said first opening, thereby forming said pocket diffusion region.

5. The method according to claim 1 wherein said oblique ion implantation process comprises the following steps:

forming a second photoresist layer on said semiconductor substrate, wherein said second photoresist layer has a second opening that exposes a portion of said light-sensing region and a portion of said gate electrode; and

obliquely implanting dopant species of said second conductivity type into said semiconductor substrate through said second opening, thereby forming said pocket diffusion region.

6. The method according to claim 1 wherein said first conductivity type is P type and said second conductivity type is N type.

7. The method according to claim 1 wherein said spacers are formed by depositing a conformal insulating layer over said semiconductor substrate, and then anisotropically dry etching said insulating layer.

8. The method according to claim 1 wherein prior to forming said gate electrode, a gate dielectric layer is formed on said semiconductor substrate, and said gate electrode is stacked on said gate dielectric layer.

9. The method according to claim 1 wherein said gate electrode comprises polysilicon, polycide and metal alloys.

10. The method according to claim 1 wherein said CMOS image sensor comprises four transistors.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 7, 2024
From: PIXART IMAGING INC.
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 068379/0918 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 20, 2005
From: CHEN, CHING-WEI; HSIEH, CHIH-CHENG; HUANG, CHIEN-CHANG
To: PIXART IMAGING INC.
Reel/Frame 016661/0258 →