Signal generating circuit capable of generating a validation signal and related method thereof
View Patent ↗A signal generating system for generating a validation signal includes: a phase lock loop (PLL) for locking an output clock to a specific clock frequency; and a digital signal generation circuit. The digital signal generating circuit includes: a triggering circuit, electrically coupled to the PLL, for determining whether the output clock of the PLL is in a frequency range, and outputting a triggering signal if the output clock is in a frequency range; and a signal generating device, electrically coupled to the triggering circuit and the PLL, for generating the validation signal according to the output clock when receiving the triggering signal; wherein before the output clock is in the frequency range, the PLL continuously outputs the output clock.
1. A signal generating system for generating a validation signal, the signal generating system comprising:
a phase lock loop (PLL) for locking an output clock to a specific clock frequency; and
a digital signal generation circuit comprising:
a triggering circuit, electrically coupled to the PLL, for determining whether the output clock of the PLL is in a frequency range, and outputting a triggering signal if the output clock is in a frequency range; and
a signal generating device, electrically coupled to the triggering circuit and the PLL, for generating the validation signal according to the output clock when receiving the triggering signal;
wherein before the output clock is in the frequency range, the PLL continuously outputs the output clock.
2. The signal generating system of claim 1 , wherein the frequency range is a working frequency range of the signal generating device.
3. The signal generating system of claim 1 , wherein the triggering circuit comprises:
a detector for determining whether the output clock is in the frequency range; and
a triggering signal generating device, electrically connected to the detector, for generating the triggering signal if the output clock is in the frequency range.
4. The signal generating system of claim 1 being utilized in a serial ATA (SATA) device.
5. The signal generating system of claim 4 , wherein the validation signal is an OOB signal.
6. The signal generating system of claim 1 being utilized in a (SAS) device.
7. The signal generating system of claim 6 , wherein the validation signal is an OOB signal.
8. The signal generating system of claim 1 being utilized in a host, wherein the validation signal is an OOB signal complying with a serial ATA (SATA) specification.
9. The signal generating system of claim 1 , wherein a frequency of the output clock is not larger than a largest frequency in the frequency range.
10. A signal generating method for generating a validation signal having a specific waveform, the signal generating method comprising:
utilizing a phase lock loop (PLL) to lock an output clock to a specific clock frequency;
detecting whether the output clock is in a frequency range;
triggering a signal generating device to generate the validation signal according to the output clock if the output clock is in the frequency range; and
before the output clock is in the frequency range, utilizing the PLL to continuously output the output clock.
11. The signal generating method of claim 10 wherein the frequency range is a working frequency range of the signal generating device.
12. The signal generating method of claim 10 being utilized in a serial ATA (SATA) device.
13. The signal generating method of claim 12 , wherein the validation signal is an OOB signal.
14. The signal generating method of claim 10 being utilized in a host, wherein the validation signal is an OOB signal complying with a serial ATA (SATA) specification.
15. The signal generating method of claim 10 , wherein a frequency of the output clock is not larger than a largest frequency in the frequency range.
16. A signal generating system for generating a validation signal, the signal generating system comprising:
a phase lock loop (PLL) for locking an output clock to a specific clock frequency; and
a digital signal generation circuit comprising:
a verifying circuit, for receiving a first signal and outputting a verifying signal if the signal complies with a predetermined condition; and
a signal generating device, electrically coupled to the verifying circuit and the PLL, for continuously generating a signal according to the output clock until receiving the verifying signal;
wherein the signal generated by the signal generating device is the validation signal when the first signal complies with the predetermined condition.
17. The signal generating system of claim 16 , wherein the verifying circuit is electrically coupled to the PLL, the first signal is the output clock, and the verifying circuit determines that the first signal complies with the predetermined condition if the output clock is in a desired frequency range.
18. The signal generating system of claim 17 , wherein the desired frequency range is a working frequency range of the signal generating device.
19. The signal generating system of claim 18 , wherein the verifying circuit comprises:
a detector, electrically coupled to the PLL, for determining whether the output clock is in the working frequency range of the signal generating device; and
a verifying signal generating device, electrically coupled to the detector, for generating the verifying signal if the output clock is in the working frequency range of the signal generating device.
20. The signal generating system of claim 16 , wherein the verifying circuit is electrically coupled to the signal generating device, the first signal is the signal outputted from the signal generating device, and the verifying circuit determines that the first signal complies with the predetermined condition if the first signal complies with a predetermined waveform of the validation signal.
21. The signal generating system of claim 20 , wherein the verifying circuit comprises:
a detector for determining whether the first signal complies with the predetermined waveform of the validation signal; and
a verifying signal generating device, electrically coupled to the detector, for generating the verifying signal if the first signal complies with the predetermined waveform of the validation signal.
22. The signal generating system of claim 16 being utilized in a serial ATA (SATA) device.
23. The signal generating system of claim 22 , wherein the validation signal is an OOB signal.
24. The signal generating system of claim 16 being utilized in an SAS device.
25. The signal generating system of claim 24 , wherein the validation signal is an OOB signal.
26. The signal generating system of claim 16 being utilized in a host, wherein the validation signal is an OOB signal complying with a serial ATA (SATA) specification.
27. A signal generating method for generating a validation signal having a predetermined waveform, the signal generating method comprising:
utilizing a phase lock loop (PLL) to lock an output clock to a specific clock frequency;
utilizing a signal generating device to generate a signal according to the output clock;
detecting whether the output clock is in a frequency range or the signal outputted from the signal generating device complies with the predetermined waveform of the validation signal; and
if the output clock is in the frequency range or the signal outputted from the signal generating device complies with the predetermined waveform, stopping the signal generating device outputting the signal.
28. The signal generating method of claim 27 , wherein the desired frequency range is a working frequency range of the signal generating device.
29. The signal generating method of claim 27 being utilized in a serial ATA (SATA) device.
30. The signal generating method of claim 29 , wherein the validation signal is an OOB signal.
31. The signal generating method of claim 27 being utilized in a host, wherein the validation signal is an OOB signal complying with a serial ATA (SATA) specification.
32. The signal generating method of claim 27 being utilized in an SAS device.
33. The signal generating method of claim 32 , wherein the validation signal is an OOB signal.