DC offset reduction circuit and method

1. An apparatus including DC offset reduction circuitry, comprising:

switching circuitry responsive to a control signal by alternately allowing and interrupting conveyance of at least one of first and second AC input signals having mutually lower and higher magnitudes, respectively;

signal mixing circuitry coupled to said switching circuitry and responsive to reception of said first and second AC input signals by providing a product signal having a magnitude with a first DC component and a first plurality of signal components related to said first and second AC input signals, wherein said signal mixing circuitry comprises Gilbert multiplier circuitry;

signal summing circuitry coupled to said signal mixing circuitry and responsive to said product signal and a DC compensation signal by providing a sum signal having a magnitude with a second DC component and said first plurality of signal components related to said first and second AC input signals; and

signal filter circuitry coupled to said signal summing circuitry and responsive to said sum signal by providing an output signal having a magnitude with a third DC component and a second plurality of signal components related to said first and second AC input signals;

wherein said DC compensation signal has a magnitude related to a sum of said first DC component and at least one of said second plurality of signal components related to said second AC input signal, and said third DC component is approximately zero.

2. A method for reducing a DC offset voltage in a product signal resulting from mixing a plurality of AC signals, comprising:

mixing first and second AC input signals having mutually lower and higher magnitudes, respectively, to produce a product signal by multiplying said first and second AC input signals with a Gilbert multiplier;

summing said product signal with a variable DC signal to produce a sum signal; and

filtering said sum signal to produce an output signal having a DC component and a plurality of signal components;

wherein

during a first time interval said first AC input signal magnitude is approximately zero and said variable DC signal is controlled to have a plurality of magnitudes in a sequence,

during said first time interval one of said plurality of variable DC signal magnitudes corresponds to a minimum magnitude of said output signal DC component, and

during a second time interval said first AC input signal magnitude is nonzero and said variable DC signal is controlled to have said one of said plurality of variable DC signal magnitudes.