Digital apparatus for soft detection of multi-chip DBPSK signals
View Patent ↗A system for implementing the soft decision of a 3-chip differential binary phase shift keying (DBPSK) optical signal using digital components. Pair-wise comparisons of three differentially detected signals are performed and analyzed by digital logic which determines the most likely sequence of data. In a first variant, pairs of adjacent data bits are detected simultaneously, whereas in a second variant, data bits are detected individually. The digital logic can be implemented using conventional logic gates.
1. A soft decision circuit for determining a most likely data content of a differential phase-shift keying (DPSK) modulated optical signal from three differentially detected intermediate signals that are based on comparisons between pairs of a series of three contiguous data bits of the DPSK modulated optical signal, the soft decision circuit comprising:
a plurality of comparators, each comparator comparing two of the three intermediate signals and generating a digital signal in accordance with the comparison; and
digital logic, the digital logic determining a most likely data content based on the comparator signals, wherein:
G= NOR[AND( B>−C, A>−B ), AND( B>A, B>C )],
where A represents a first of the intermediate signals based on a comparison between the first and second of the series of three contiguous data bits, B represents a second of the intermediate signals based on a comparison between the second and third of the series of three contiguous data bits, C represents a third of the intermediate signals based on a comparison between the first and third of the series of three contiguous data bits, and G represents the most likely data content.
2. The soft decision circuit of claim 1 , wherein the DPSK signal is a differential binary phase-shift keying (DBPSK) signal.
3. The soft decision circuit of claim 1 , wherein the plurality of comparators includes four comparators and the digital logic includes two AND gates coupled to the four comparators and a NOR gate coupled to the two AND gates.
4. A soft detection circuit comprising the soft decision circuit of claim 1 .
5. The soft detection circuit of claim 4 comprising:
a three-chip DPSK detection circuit, wherein the three-chip DPSK detection circuit generates the three differentially detected intermediate signals.
6. The soft detection circuit of claim 5 , wherein at least one of the three differentially detected intermediate signals is attenuated according to a weighting factor.
7. A soft decision circuit for determining a most likely data content of a differential phase-shift keying (DPSK) modulated optical signal from three differentially detected intermediate signals that are based on comparisons between pairs of a series of three contiguous data bits of the DPSK modulated optical signal, the soft decision circuit comprising:
a plurality of comparators, each comparator comparing two of the three intermediate signals and generating a digital signal in accordance with the comparison; and
digital logic, the digital logic determining a most likely data content based on the comparator signals, wherein the digital logic selects the largest of a plurality of decision variables q ij , wherein;
q 00 =A+B+C,
q 01 =−A+B−C,
q 10 =A−B−C,
q 11 =−A−B+C,
where A represents a first of the intermediate signals based on a comparison between the first and second of the series of three contiguous data bits, B represents a second of the intermediate signals based on a comparison between the second and third of the series of three contiguous data bits, C represents a third of the intermediate signals based on a comparison between the first and third of the series of three contiguous data bits, and q ij represents the likelihood of a bit sequence ij.
8. The soft decision circuit of claim 7 , wherein the DPSK signal is a differential binary phase-shift keying (DBPSK) signal.
9. A soft detection circuit comprising the soft decision circuit of claim 7 .
10. The soft detection circuit of claim 9 comprising:
a three-chip DPSK detection circuit, wherein the three-chip DPSK detection circuit generates the three differentially detected intermediate signals.
11. The soft detection circuit of claim 10 , wherein at least one of the three differentially detected intermediate signals is attenuated according to a weighting factor.
12. A soft decision circuit for determining a most likely data content of a differential phase-shift keying (DPSK) modulated optical signal from three differentially detected intermediate signals that are based on comparisons between pairs of a series of three contiguous data bits of the DPSK modulated optical signal, the soft decision circuit comprising:
a plurality of comparators, each comparator comparing two of the three intermediate signals and generating a digital signal in accordance with the comparison; and
digital logic, the digital logic determining a most likely data content based on the comparator signals, wherein;
G 1=NOR[AND( A>−B, B>−C ), AND( B>A, B>C )],
G 2=NOR[AND( A>−B, A>−C ), AND(NOT( B>A ), A>C )],
where A represents a first of the intermediate signals based on a comparison between the first and second of the series of three contiguous data bits, B represents a second of the intermediate signals based on a comparison between the second and third of the series of three contiguous data bits, C represents a third of the intermediate signals based on a comparison between the first and third of the series of three contiguous data bits, G 1 represents a first bit of the most likely data content and G 2 represents a second bit of the most likely data content.
13. A soft detection circuit comprising the soft decision circuit of claim 12 .
14. The soft detection circuit of claim 13 comprising:
a three-chip differential phase-shift-keying (DPSK) detection circuit, wherein the three-chip DPSK detection circuit generates the three differentially detected intermediate signals.
15. The soft detection circuit of claim 14 , wherein at least one of the three differentially detected intermediate signals is attenuated according to a weighting factor.
16. The soft decision circuit of claim 12 , wherein the DPSK signal is a differential binary phase-shift keying (DBPSK) signal.
17. The soft decision circuit of claim 12 , wherein the plurality of comparators includes six comparators and the digital logic includes four AND gates coupled to the six comparators, and two NOR gates coupled to the four AND gates.
18. The soft decision circuit of claim 17 , comprising an interleaver coupled to the NOR gates.
19. A soft detection circuit comprising:
a three-chip differential phase-shift keying (DPSK) detection circuit, wherein the three-chip DPSK detection circuit generates a plurality of differentially detected intermediate signals based on comparisons between pairs of a series of three contiguous data bits of a DPSK modulated optical signal and wherein one of the three differentially detected intermediate signals is based on a comparison between the first and third of the series of three contiguous data bits and said one of the three differentially detected intermediate signals is attenuated according to a weighting factor; and
a soft decision circuit for determining a most likely data content of the DPSK modulated optical signal from the plurality of differentially detected intermediate signals, the soft decision circuit including:
a plurality of comparators, each comparator comparing two of the plurality of intermediate signals and generating a digital signal in accordance with the comparison; and
digital logic, the digital logic determining a most likely data content based on the comparator signals.
20. The soft detection circuit of claim 19 , wherein the weighting factor is approximately 0.5.
21. The soft detection circuit of claim 19 , wherein the DPSK signal is a differential binary phase-shift keying (DBPSK) signal.