On-device data compression to increase speed and capacity of flash memory-based mass storage devices
View Patent ↗A mass storage device having at least one flash memory device and DRAM or SRAM-based cache within a package, and which comprises a co-processor within the package for performing compression and decompression of cached data before writing the cached data to the flash memory device.
1. A mass storage device having at least one flash memory device and DRAM or SRAM-based cache within a package, the flash memory device being readable and programmable in bytes in a random access fashion and erased and reprogrammed in blocks, the mass storage device comprising co-processor means within the package for performing hardware-based compression of cached data before writing the cached data to the flash memory device in random access fashion and performing hardware-based decompression of data read from the flash memory device in random access fashion.
2. The mass storage device according to claim 1 , wherein at least one flash memory device comprises an EEPROM.
3. The mass storage device according to claim 1 , wherein the mass storage device has a higher write speed capability than would be possible if the mass storage device did not comprise the co-processor means.
4. The mass storage device according to claim 1 , wherein the mass storage device has a higher read speed capability than would be possible if the mass storage device did not comprise the co-processor means.
5. The mass storage device according to claim 1 , further comprising a USB interface device.
6. The mass storage device according to claim 1 . wherein the cache is DRAM-based.
7. The mass storage device according to claim 1 , wherein the cache is SRAM-based.
8. The mass storage device according to claim 1 , wherein the cache comprises write cache.
9. The mass storage device according to claim 1 , wherein the cache comprises read cache.
10. The mass storage device according to claim 1 , wherein the co-processor means comprises prefetch scheduler means.
11. A mass storage device comprising:
a package;
at least one flash memory device comprising an EEPROM within the package, the flash memory device being readable and programmable in bytes in a random access fashion and erased and reprogrammed in blocks;
DRAM or SRAM-based cache within the package;
a USB interface device on the package for interconnecting the mass storage device to a USB port; and
co-processor means within the package for performing hardware-based compression of cached data before writing the cached data to the flash memory device in a random access fashion and performing hardware-based decompression of data read from the flash memory device in a random access fashion.
12. The mass storage device according to claim 11 , wherein the mass storage device has a higher write speed capability than would be possible if the mass storage device did not comprise the co-processor means.
13. The mass storage device according to claim 11 , wherein the mass storage device has a higher read speed capability than would be possible if the mass storage device did not comprise the co-processor means.
14. The mass storage device according to claim 11 , wherein the cache is DRAM-based.
15. The mass storage device according to claim 11 , wherein the cache is SRAM-based.
16. The mass storage device according to claim 11 , wherein the cache comprises write cache.
17. The mass storage device according to claim 11 , wherein the cache comprises read cache.
18. The mass storage device according to claim 11 , wherein the co-processor means comprises prefetch scheduler means.