INTEGRATED SRAM CACHE FOR A MEMORY MODULE AND METHOD THEREFOR
A memory module having at least one random access memory device and a memory bus on a substrate. The memory module further comprises an SRAM cache interfaced with the random access memory device through an ASIC associated with the SRAM cache and operable as a prefetch controller for the SRAM cache. The ASIC and SRAM cache cooperate to enable data to be prefetched and cached during idle cycles of the memory device, thereby increasing the overall operating speed of the memory circuit by minimizing latencies should the prefetched data be requested. The ASIC can be programmed to prefetch not only data from the originally accessed row during a read operation, but also to speculatively prefetch data from logically coherent rows in order to anticipate and counteract a page miss and the associated latencies based on the locality of data.
1 . A memory module comprising at least one random access memory device and a memory bus on a substrate, the memory module comprising an SRAM cache interfaced with the random access memory device through an ASIC associated with the SRAM cache and operable as a prefetch controller for the SRAM cache.
2 . The memory module according to claim 1 , wherein the ASIC is operable to prefetch data into the SRAM cache during an idle period following a page access so that the prefetched data are accessible with minimal latencies.
3 . The memory module according to claim 2 , wherein the SRAM cache buffers cache lines from a CPU in communication with the memory module.
4 . The memory module according to claim 1 , wherein the ASIC is programmed to prefetch data from a first accessed row and also speculatively prefetch data from at least one logically coherent row of the first accessed row.
5 . The memory module according to claim 1 , wherein the random access memory device is a DRAM device.
6 . The memory module according to claim 1 , wherein the SRAM cache is configured for porting to the memory bus in a format other than a 64-bit memory bus.
7 . The memory module according to claim 1 , wherein the SRAM cache is configured so that command signals at the random access memory device are independent from a supply voltage signal supplied to the random access memory device through the memory bus.
8 . The memory module according to claim 1 , wherein the memory bus is a full duplex memory bus that allows interspersed write commands within a read sequence of the random access memory device.
9 . The memory module according to claim 8 , wherein the SRAM cache is a dual-ported SRAM cache.
10 . A process of accessing data from at least one random access memory device of a memory module, the process comprising:
activating a bank of memory cells of the random access memory device;
issuing a read command comprising row and column address select commands to the bank of memory cells;
during an idle cycle following the read command, performing a prefetch operation to prefetch data into a SRAM cache so that the prefetched data are accessible with minimal latencies; and
direct reading from the SRAM cache in response to a second read command.
11 . The process according to claim 10 , wherein the prefetched data comprises data from a first accessed row of the random access memory device and also speculatively prefetched data from at least one logically coherent row of the first accessed row.
12 . The process according to claim 10 , further comprising using the SRAM cache to buffer cache lines from a CPU in communication with the memory module.
13 . The process according to claim 10 , wherein the random access memory device is a DRAM device.
14 . The process according to claim 10 , wherein the SRAM cache ports to a memory bus of the memory module in a format other than a 64-bit memory bus.
15 . The process according to claim 10 , wherein the SRAM cache is configured so that command signals at the random access memory device are independent from a supply voltage signal supplied to the random access memory device through a memory bus of the memory module.
16 . The process according to claim 10 , wherein the memory module comprises a full duplex memory bus and interspersed write commands occur within a read sequence of the random access memory device.
17 . The process according to claim 16 , wherein the SRAM cache is a dual-ported SRAM cache.