IP Library › Granted Patent US 7,295,028
Granted Patent B2
US 7,295,028 · App. 11/166,345 · Granted Nov 13, 2007

Semiconductor integrated circuit and memory test method

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Quick Facts
Patent No.
US 7,295,028
App. No.
11/166,345
Granted
Nov 13, 2007
Kind
B2
Abstract

The present invention provides a semiconductor integrated circuit capable of testing a high-speed memory at the actual operation speed of the memory even when the operation speed of the built-in self-test circuit of the integrated circuit is restricted. In order to test a memory operating on a first clock, the integrated circuit is provided with a first test pattern generation section, operating on a second clock, for generating test data, and a second test pattern generation section, operating on a third clock, the inverted clock of the second clock, for generating test data. Furthermore, the integrated circuit is provided with a test data selection section for selectively outputting either the test data output from the first test pattern generation section or the test data output from the second test pattern generation section depending on the signal value of the second clock, thereby inputting the test data to the memory as test data. The frequency of the second clock is lower than, for example, one quarter or one half, the frequency of the first clock.

Claims (96)

1. A semiconductor integrated circuit comprising:

a memory operating on a first clock,

a first test pattern generation section, operating on a second clock having one quarter the frequency of said first clock, for generating first test data,

a second test pattern generation section, operating on a third clock, the inverted clock of said second clock, for generating second test data, and

a test data selection section for selectively outputting either said first or second test data being output from said first test pattern generation section or said second test pattern generation section, respectively, depending on either the signal value of said second clock or the signal value of said third clock, thereby inputting the selected test data to said memory as third test data.

2. A semiconductor integrated circuit comprising:

a memory operating on a first clock,

a first test pattern generation section, operating on a second clock having one quarter the frequency of said first clock, for generating first test data,

a second test pattern generation section, operating on a third clock, the inverted clock of said second clock, for generating second test data, and

a test data selection section for selectively outputting either said first or second test data being output from said first test pattern generation section or said second test pattern generation section, respectively, depending on a control signal supplied from outside of the semiconductor integrated circuit, thereby inputting the selected test data to said memory as third test data.

3. A semiconductor integrated circuit comprising:

a memory operating on a first clock,

a first test pattern generation section, operating on a second clock having one quarter the frequency of said first clock, for generating first test data,

a second test pattern generation section, operating on said second clock, for generating second test data, and

a test data selection section for selectively outputting either said first or second test data being output from said first test pattern generation section or said second test pattern generation section, respectively, depending on the signal value of said second clock, thereby inputting the selected test data to said memory as third test data.

4. A semiconductor integrated circuit comprising:

a memory operating on a first clock,

a first test pattern generation section, operating on a second clock having one quarter the frequency of said first clock, for generating first test data,

a second test pattern generation section, operating on said second clock, for generating second test data, and

a test data selection section for selectively outputting either said first or second test data being output from said first test pattern generation section or said second test pattern generation section, respectively, depending on a control signal supplied from outside of the semiconductor integrated circuit, thereby inputting the selected test data to said memory as third test data.

5. A semiconductor integrated circuit comprising:

a double data rate memory operating on a first clock,

a first test pattern generation section, operating on a second clock having half the frequency as that of said first clock, for generating first test data,

a second test pattern generation section, operating on a third clock, the inverted clock of said second clock, for generating second test data, and

a test data selection section for selectively outputting either said first or second test data being output from said first test pattern generation section or said second test pattern generation section, respectively, depending on either the signal value of said second clock or the signal value of said third clock, thereby inputting the selected test data to said double data rate memory as third test data.

6. A semiconductor integrated circuit comprising:

a double data rate memory operating on a first clock,

a first test pattern generation section, operating on a second clock having half the frequency as that of said first clock, for generating first test data,

a second test pattern generation section, operating on a third clock, the inverted clock of said second clock, for generating second test data, and

a test data selection section for selectively outputting either said first or second test data being output from said first test pattern generation section or said second test pattern generation section, respectively, depending on a control signal supplied from outside of the semiconductor integrated circuit, thereby inputting the selected test data to said double data rate memory as third test data.

7. A semiconductor integrated circuit comprising:

a double data rate memory operating on a first clock,

a first test pattern generation section, operating on a second clock having half the frequency of that of said first clock, for generating first test data,

a second test pattern generation section, operating on said second clock, for generating second test data, and

a test data selection section for selectively outputting either said first or second test data being output from said first test pattern generation section or said second test pattern generation section, respectively, depending on the signal value of said second clock, thereby inputting the selected test data to said double data rate memory as third test data.

8. A semiconductor integrated circuit comprising:

a double data rate memory operating on a first clock,

a first test pattern generation section, operating on a second clock having half the frequency of that of said first clock, for generating first test data,

a second test pattern generation section, operating on said second clock, for generating second test data, and

a test data selection section for selectively outputting either said first or second test data being output from said first test pattern generation section or said second test pattern generation section, respectively, depending on a control signal supplied from outside of the semiconductor integrated circuit, thereby inputting the selected test data to said double data rate memory as third test data.

9. A method of testing a memory operating on a first clock, comprising the steps of generating first test data depending on a second clock having one quarter the frequency of said first clock, generating second test data depending on a third clock, the inverted clock of said second clock, selecting either said first or second test data depending on either the signal value of said second clock or the signal value of said third clock, and inputting the selected test data to said memory as third test data.

10. A method of testing a memory operating on a first clock, comprising the steps of generating first test data depending on a second clock having one quarter the frequency of said first clock, generating second test data depending on a third clock, the inverted clock of said second clock, selecting either said first or second test data depending on a control signal supplied from outside of the semiconductor integrated circuit, and inputting the selected test data to said memory as third test data.

11. A method of testing a double data rate memory operating on a first clock, comprising the steps of generating first test data depending on a second clock having half the frequency as that of said first clock, generating second test data depending on a third clock, the inverted clock of said second clock, selecting either said first or second test data depending on either the signal value of said second clock or the signal value of said third clock, and inputting the selected test data to said double data rate memory as third test data.

12. A method of testing a double data rate memory operating on a first clock, comprising the steps of generating first test data depending on a second clock having half the frequency as that of said first clock, generating second test data depending on a third clock, the inverted clock of said second clock, selecting either said first or second test data depending on a control signal supplied from outside of the semiconductor integrated circuit, and inputting the selected test data to said double data rate memory as third test data.

13. A method of testing a memory operating on a first clock, comprising the steps of generating first test data depending on a second clock having one quarter the frequency of said first clock, generating second test data depending on said second clock, selecting either said first or second test data depending on the signal value of said second clock, and inputting the selected test data to said memory as third test data.

14. A method of testing a memory operating on a first clock, comprising the steps of generating first test data depending on a second clock having one quarter the frequency of said first clock, generating second test data depending on said second clock, selecting either said first or second test data depending on a control signal supplied from outside of the semiconductor integrated circuit, and inputting the selected test data to said memory as third test data.

15. A method of testing a double data rate memory operating on a first clock, comprising the steps of generating first test data depending on a second clock having half the frequency as that of said first clock, generating second test data depending on said second clock, selecting either said first or second test data depending on the signal value of said second clock, and inputting the selected test data to said double data rate memory as third test data.

16. A method of testing a double data rate memory operating on a first clock, comprising the steps of generating first test data depending on a second clock having half the frequency as that of said first clock, generating second test data depending on said second clock, selecting either said first or second test data depending on a control signal supplied from outside of the semiconductor integrated circuit, and inputting the selected test data to said double data rate memory as third test data.

17. A semiconductor integrated circuit comprising:

a memory operating on a first clock,

a first test pattern generation section, operating on a second clock having a lower frequency than the frequency of said first clock, for generating first test data,

a second test pattern generation section, operating on a third clock, the inverted clock of said second clock, for generating second test data, and

a test data selection section for selectively outputting either said first or second test data being output from said first test pattern generation section or said second test pattern generation section, respectively, depending on either the signal value of said second clock or the signal value of said third clock, thereby inputting the selected test data to said memory as third test data.

18. A semiconductor integrated circuit comprising:

a memory operating on a first clock,

a first test pattern generation section, operating on a second clock having one quarter the frequency of said first clock, for generating first test data,

a second test pattern generation section, operating on a third clock, the inverted clock of said second clock, for generating second test data, and

a test data selection section for selectively outputting either said first or second test data being output from said first test pattern generation section or said second test pattern generation section, respectively, depending on a control signal made from said second clock, thereby inputting the selected test data to said memory as third test data.

19. A semiconductor integrated circuit comprising:

a memory operating on a first clock,

a first test pattern generation section, operating on a second clock having a lower frequency than the frequency of said first clock, for generating first test data,

a second test pattern generation section, operating on said second clock, for generating second test data, and

a test data selection section for selectively outputting either said first or second test data being output from said first test pattern generation section or said second test pattern generation section, respectively, depending on the signal value of said second clock, thereby inputting the selected test data to said memory as third test data.

20. A semiconductor integrated circuit comprising:

a memory operating on a first clock,

a first test pattern generation section, operating on a second clock having one quarter the frequency of said first clock, for generating first test data,

a second test pattern generation section, operating on said second clock, for generating second test data, and

a test data selection section for selectively outputting either said first or second test data being output from said first test pattern generation section or said second test pattern generation section, respectively, depending on a control signal made from said second clock, thereby inputting the selected test data to said memory as third test data.

21. A semiconductor integrated circuit comprising:

a double data rate memory operating on a first clock,

a first test pattern generation section, operating on a second clock having a lower frequency than that of said first clock, for generating first test data,

a second test pattern generation section, operating on a third clock, the inverted clock of said second clock, for generating second test data, and

a test data selection section for selectively outputting either said first or second test data being output from said first test pattern generation section or said second test pattern generation section, respectively, depending on either the signal value of said second clock or the signal value of said third clock, thereby inputting the selected test data to said double data rate memory as third test data.

22. A semiconductor integrated circuit comprising:

a double data rate memory operating on a first clock,

a first test pattern generation section, operating on a second clock having half the frequency as that of said first clock, for generating first test data,

a second test pattern generation section, operating on a third clock, the inverted clock of said second clock, for generating second test data, and

a test data selection section for selectively outputting either said first or second test data being output from said first test pattern generation section or said second test pattern generation section, respectively, depending on a control signal made from said second clock, thereby inputting the selected test data to said double data rate memory as third test data.

23. A semiconductor integrated circuit comprising:

a double data rate memory operating on a first clock,

a first test pattern generation section, operating on a second clock having a lower frequency than that of said first clock, for generating first test data,

a second test pattern generation section, operating on said second clock, for generating second test data, and

a test data selection section for selectively outputting either said first or second test data being output from said first test pattern generation section or said second test pattern generation section, respectively, depending on the signal value of said second clock, thereby inputting the selected test data to said double data rate memory as third test data.

24. A semiconductor integrated circuit comprising:

a double data rate memory operating on a first clock,

a first test pattern generation section, operating on a second clock having half the frequency of that of said first clock, for generating first test data,

a second test pattern generation section, operating on said second clock, for generating second test data, and

a test data selection section for selectively outputting either said first or second test data being output from said first test pattern generation section or said second test pattern generation section, respectively, depending on a control signal made from said second clock, thereby inputting the selected test data to said double data rate memory as third test data.

25. A method of testing a memory operating on a first clock, comprising the steps of generating first test data depending on a second clock having a lower frequency than that of said first clock, generating second test data depending on a third clock, the inverted clock of said second clock, selecting either said first or second test data depending on either the signal value of said second clock or the signal value of said third clock, and inputting the selected test data to said memory as third test data.

26. A method of testing a memory operating on a first clock, comprising the steps of generating first test data depending on a second clock having one quarter the frequency of said first clock, generating second test data depending on a control signal made from said second clock, selecting either said first or second test data depending on a control signal supplied from outside of the semiconductor integrated circuit, and inputting the selected test data to said memory as third test data.

27. A method of testing a double data rate memory operating on a first clock, comprising the steps of generating first test data depending on a second clock having a lower frequency than that of said first clock, generating second test data depending on a third clock, the inverted clock of said second clock, selecting either said first or second test data depending on either the signal value of said second clock or the signal value of said third clock, and inputting the selected test data to said double data rate memory as third test data.

28. A method of testing a double data rate memory operating on a first clock, comprising the steps of generating first test data depending on a second clock having half the frequency as that of said first clock, generating second test data depending on a third clock, the inverted clock of said second clock, selecting either said first or second test data depending on a control signal made from said second clock, and inputting the selected test data to said double data rate memory as third test data.

29. A method of testing a memory operating on a first clock, comprising the steps of generating first test data depending on a second clock having a lower frequency than that of said first clock, generating second test data depending on said second clock, selecting either said first or second test data depending on the signal value of said second clock, and inputting the selected test data to said memory as third test data.

30. A method of testing a memory operating on a first clock, comprising the steps of generating first test data depending on a second clock having one quarter the frequency of said first clock, generating second test data depending on said second clock, selecting either said first or second test data depending on a control signal made from said second clock, and inputting the selected test data to said memory as third test data.

31. A method of testing a double data rate memory operating on a first clock, comprising the steps of generating first test data depending on a second clock having a lower frequency than that of said first clock, generating second test data depending on said second clock, selecting either said first or second test data depending on the signal value of said second clock, and inputting the selected test data to said double data rate memory as third test data.

32. A method of testing a double data rate memory operating on a first clock, comprising the steps of generating first test data depending on a second clock having half the frequency as that of said first clock, generating second test data depending on said second clock, selecting either said first or second test data depending on a control signal made from said second clock, and inputting the selected test data to said double data rate memory as third test data.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 26, 2014
From: PANASONIC CORPORATION
To: COLLABO INNOVATIONS, INC.
Reel/Frame 033021/0806 →
LIEN Recorded Jan 13, 2014
From: COLLABO INNOVATIONS, INC.
To: PANASONIC CORPORATION
Reel/Frame 031997/0445 →
CHANGE OF NAME Recorded Jan 8, 2014
From: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
To: PANASONIC CORPORATION
Reel/Frame 031947/0358 →