Integrated circuit with memory-less page table
View Patent ↗A system is disclosed that comprises a processor, a memoryless first level page table addressable by the processor, and a second level page table stored in a memory coupled to the processor. The second level page table is addressable by at least one entry of the first level page table.
1. A system comprising:
a processor;
a memoryless first level page table addressable by the processor, wherein the memoryless first level page table comprises:
a first multiplexer coupled to the processor;
a plurality of address modules coupled to the first multiplexer; and
a second multiplexer coupled to the first multiplexer to determine a memory address mode for the first multiplexer; and
a second level page table stored in a memory coupled to the processor;
wherein the memoryless first level page table comprises a plurality of entries; and
wherein the plurality of entries comprises at least one of a direct address and a second level page table address, wherein an entry of the memoryless first level page table that is a direct address is accessed and evaluated to determine whether the accessed entry is found within the second level page table before the accessed entry returns data stored in the memory.
2. The system of claim 1 , wherein at least one of the plurality of address modules comprises a plurality of data segments, a first portion of the plurality of data segments held at a constant address value by a set of logic gates and a second portion of the plurality of data segments responsive to a plurality of flip-flops, wherein a digital logic state of each of the plurality of flip-flops is selectable by the processor.
3. The system of claim 2 , wherein at least one of the plurality of address modules is associated with a memory location and wherein a digital logic state of at least one of the plurality of flip-flops is representative of a cacheable state of the memory location.
4. The system of claim 3 , wherein the digital logic state of at least one of the plurality of flip-flops is representative of a memory access mode.
5. The system of claim 4 , wherein the memory access mode is a one of a coarse mode and a fine mode.
6. The system of claim 2 , wherein the memoryless first level page table comprises a plurality of entries, and at least one of the plurality of entries is a predetermined constant binary value.
7. The system of claim 6 , wherein at least one of the plurality of entries is determined based on at least one of the plurality of flip-flops.
8. The system of claim 1 , wherein the memory address mode is selected from one of an error mode, a coarse mode, a fine mode, and a section mode.
9. The system of claim 1 , wherein the second multiplexer is used to determine a selection for the first multiplexer.
10. The system of claim 9 , wherein the selection is one of a direct address and a second level page table address.
11. The system of claim 1 , wherein the second level page table stores a plurality of physical memory addresses of a computer readable memory.
12. The system of claim 11 , further comprising the computer readable memory.
13. The system of claim 12 , further comprising a memory bus coupled to the computer readable memory.
14. A method comprising:
receiving a memory address from a memoryless first level page table, wherein the memoryless first level page table comprises:
a first multiplexer coupled to a processor
a plurality of address modules coupled to the first multiplexer; and
a second multiplexer coupled to the first multiplexer to determine a memory address mode for the first multiplexer;
accessing an entry in a second level page table that is stored at a data location in a memory device when the memory address references an unavailable memory location; and
accessing the data location in the memory device based on the memory address when the memory address references an available memory location, and wherein when the memory address is a direct address the memory address is evaluated to determine whether the memory address is found within the second level page table before the data location in the memory device is accessed.
15. The method of claim 14 , wherein the memory address is hard wired.
16. The method of claim 14 , wherein at least a portion of the memory address is stored by a plurality of flip-flops.
17. The method of claim 14 , wherein the memory address is selected from a plurality of predetermined first level page table addresses, at least one of the predetermined first level page table addresses representative of an unavailable memory location.
18. A method comprising:
providing a first address to a memoryless first level page table, wherein the memoryless first level page table comprises:
a first multiplexer coupled to a processor;
a plurality of address modules coupled to the first multiplexer; and
a second multiplexer coupled to the first multiplexer to determine a memory address mode for the first multiplexer;
receiving a second address from the memoryless first level page table;
locating the second address after determining that the second address represents an available memory location in a memory, wherein when the second address is a direct address the second address is evaluated to determine whether the second address is found within a second level page table before the evaluated second address returns data stored in the memory; and
locating an entry in the second level page table stored in the memory after determining that the second address represents an unavailable memory location.
19. The method of claim 18 , further comprising identifying the entry in the second level page table as a third address.
20. The method of claim 18 , wherein the second address is selected from a plurality of page addresses, wherein at least one of the plurality of page addresses represents an unavailable memory location.
21. The method of claim 18 , further comprising:
providing a memory address mode control signal to the memoryless first level page table.
22. The method of claim 18 , wherein the first address is provided to a selection input of the first multiplexer and wherein the first multiplexer provides the second address.
23. A system comprising:
a processor;
a bus coupled to the processor;
a memory mapping module coupled to the bus, the memory mapping module including a first input to receive a virtual memory address, the mapping module including a memoryless first level page table, the mapping module having an output to provide a memory address, wherein the memoryless first level page table comprises:
a first multiplexer coupled to the processor;
a plurality of address modules coupled to the first multiplexer; and
a second multiplexer coupled to the first multiplexer to determine a memory address mode for the first multiplexer;
a memory device responsive to the memory mapping module; and
a second level page table stored in the memory device, wherein the memory address is one of a fixed direct memory address and a pointer to a data location in the second level page table, wherein when the memory address is a fixed direct memory address the fixed direct memory address is evaluated to determine whether the fixed direct memory address is found within the second level page table before the fixed direct memory address returns data stored in the memory device.
24. The system of claim 23 , wherein the memoryless first level page table has a larger address space than the second level page table.
25. The system of claim 23 , wherein the second level page table is uncompressed.
26. The system of claim 23 , wherein the second level page table is stored in less than one percent of a memory capacity of the memory device.
27. The system of claim 23 , wherein the first level page table is capable of addressing a memory space of a first size, and wherein the memory device has a memory capacity of a second size, the first size greater than 5% of the second size.