Thin film transistor array panel and manufacturing method thereof
View Patent ↗Gate lines and a gate shorting bar connected to the gate lines, which include lower and upper films, are formed on a substrate. A gate insulating layer, semiconductors, and ohmic contacts are formed in sequence. Data lines and a data shorting bar connected to the data lines, which include lower and upper films, are formed thereon. A passivation layer is formed on the data lines and the data shorting bar. The passivation layer and the gate insulating are patterned to form contact holes exposing the lower films of the gate lines and the data lines. Connecting portions of the gate lines and the data lines for connection with driving circuits are locate opposite the shorting bars with respect to the contact holes.
1. A thin film transistor array panel comprising:
an insulating substrate including edges;
a plurality of gate lines formed on the insulating substrate and including gate pads, wherein a first edge of the insulating substrate is nearest from the gate pads among the edges of the insulating substrate;
a gate insulating layer formed on the gate lines;
a semiconductor layer formed on the gate insulating layer;
a plurality of data lines formed at least in part on the semiconductor layer and including data pads, wherein a second edge of the insulating substrate is nearest from the data pads among the edges of the insulating substrate;
a plurality of drain electrodes formed at least in part on the semiconductor layer;
a plurality of pixel electrodes connected to the drain electrodes; and
a plurality of discharging units, each of the discharging units located between the first edge and the gate pad, or between the second edge and the data pad.
2. The thin film transistor array panel of claim 1 , wherein the discharging units comprise a plurality of protective members connected to extensions of the gate lines or the data lines.
3. The thin film transistor array panel of claim 2 , further comprising a passivation layer disposed between the data lines and the gate lines, and the pixel electrodes; and
wherein the passivation layer comprises a plurality of first contact holes through which the protective members are connected to the extensions of the gate lines or the data lines.
4. The thin film transistor array panel of claim 3 , wherein the pixel electrodes are the same layer as the protective members.
5. The thin film transistor array panel of claim 3 , wherein each of the extensions of the gate lines or the data lines that are connected to the protective members comprises a lower layer and an upper layer having lower resistivity than the lower layer, the first contact holes exposing the lower layers, and the protective members are directly connected to the lower layers through the first contact holes.
6. The thin film transistor array panel of claim 3 , wherein the pixel electrodes overlap one of the gate lines and the data lines.
7. The thin film transistor array panel of claim 3 , wherein the pixel electrodes overlap the previous gate lines to make storage capacitors.
8. The thin film transistor array panel of claim 7 , further comprising a plurality of conductive patterns respectively connecting the pixel electrode and overlapping the previous gate lines.
9. The thin film transistor array panel of claim 3 , further comprising a storage electrode line overlapping the pixel electrodes.
10. The thin film transistor array panel of claim 9 , wherein the drain electrodes overlap the storage electrode lines.
11. The thin film transistor array panel of claim 9 , wherein the passivation layer has a plurality of second contact holes respectively connecting the drain electrodes and the pixel electrodes, and the contact holes overlap the storage electrode line.