System and method for high precision clock recovery over packet networks
View Patent ↗An innovative system and method for achieving high precision clock recovery, i.e. reconstruction of the clock signal having the same frequency, over a packet switched network. The proposed method utilizes a minimum network delay approach, which overcomes the problems caused by delay variation of the network and filters out network jitter, such as noise jitter and other “singular” anomalies causing latency deviations. Minimum network delay is defined herein as the time delay in which a packet remains in the network under assumption that all transmission queues through which the packet passes are empty.
1. A method for high precision clock recovery over a packet switched network, said method comprising the steps of:
generating packets at a local unit carrying information to a remote unit using a local clock signal, wherein each generated packet carries a transmitted timestamp;
generating a remote timestamp at said remote unit for each said generated packet;
providing a minimum network delay estimation for filtering out network jitter, wherein said minimum network delay estimation is defined as a time delay in which a packet remains in the packet switched network, assuming that all transmission queues through which said packet passes through are empty;
reconstructing a received clock signal based on a time difference between said transmitted timestamp and said remote timestamp; and
providing a latency estimation for detecting minimum delay values, wherein each of said minimum delay values is said time difference between said transmitted timestamp and said remote timestamp over a time window,
wherein said latency deviation estimation comprises the steps of:
obtaining an array containing 2N last minimum delay values, wherein N is an integer number;
applying two linear regression procedures on said array, wherein a first regression procedure is applied on N first minimum delay values and a second regression procedure is applied on N last minimum delay values;
calculating middle height difference of each of said two regression procedures; and
detecting a latency deviation occurrence by checking whether said middle height difference is continuously increased x times and then continuously decreased y times, wherein x and y are threshold values, wherein a latency deviation value is defined as a peak value received from said two regression procedures.
2. The method of claim 1 further comprising the step of building at least one high frequency reference clock.
3. The method of claim 1 further comprising the step of converting each of said minimum delay values into a control word for obtaining an accurate received clock signal.
4. The method of claim 1 , wherein providing said minimum network delay estimation step includes noise jitter and other “singular” anomalies causing latency deviations.
5. A system for high precision clock recovery over a packet switched network, said system comprising:
means for generating packets at a local unit carrying information to a remote unit using a local clock signal, wherein each generated packet carries a transmitted timestamp;
means for generating a remote timestamp at said remote unit for each said generated packet;
means for obtaining minimum network delay estimation for filtering out network jitter, wherein said minimum network delay estimation is defined as a time delay in which a packet remains in the packet switched network, assuming that all transmission queues through which Said packet passes through are empty;
means for reconstructing a received clock signal based on a time difference between said transmitted timestamp and said remote timestamp; and
means for detecting minimum delay values, wherein each of said minimum delay values is defined as a latency estimation being said time difference between said transmitted timestamp and said remote timestamp over a time window,
wherein said means for obtaining said latency deviation estimation operates in accordance with the steps of:
obtaining an array containing 2N last minimum delay values, wherein N is an integer number;
applying two linear regression procedures on said array, wherein a first regression procedure is applied on N first minimum delay values and a second regression procedure is applied on N last minimum delay values;
calculating middle height difference of each of said two regression procedures; and
detecting a latency deviation occurrence by checking whether said middle height difference is continuously increased x times and then continuously decreased y times, wherein x and y are threshold values, wherein a latency deviation value is defined as a peak value received from said two regression procedures.
6. The system of claim 5 further comprising at least one high frequency reference clock.
7. The system of claim 5 further comprising means for converting each of said minimum delay values into a control word for obtaining an accurate received clock signal.
8. The system of claim 5 , wherein said providing said minimum network delay estimation step includes noise jitter and other “singular” anomalies causing latency deviations.